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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [nvram/] [nvram.c] - Blame information for rev 30

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/*
 *  This file contains the NvRAM driver for the PPCn_60x
 *
 *  COPYRIGHT (c) 1998 by Radstone Technology
 *
 *
 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
 *
 * You are hereby granted permission to use, copy, modify, and distribute
 * this file, provided that this notice, plus the above copyright notice
 * and disclaimer, appears in all copies. Radstone Technology will provide
 * no support for this code.
 *
 */
 
#include <bsp.h>
#include "ds1385.h"
#include "mk48t18.h"
#include "stk11c68.h"
 
/*
 * Private types
 */
typedef
void
(*PNVRAMWRITE)
(
        unsigned32 ulOffset,
        unsigned8 ucByte
);
 
typedef
unsigned8
(*PNVRAMREAD)
(
        unsigned32 ulOffset
);
 
typedef
void
(*PNVRAMCOMMIT)
(
);
 
typedef struct _NVRAM_ENTRY_TABLE
{
        PNVRAMWRITE     nvramWrite;
        PNVRAMREAD      nvramRead;
        PNVRAMCOMMIT    nvramCommit;
        unsigned32      nvramSize;
} NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE;
 
/*
 * Private routines
 */
 
/*
 * This routine provides a stub for NvRAM devices which
 * do not require a commit operation
 */
static void nvramCommitStub();
 
/*
 * DS1385 specific routines
 */
static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucByte);
static unsigned8 nvramDsRead(unsigned32 ulOffset);
 
/*
 * MK48T18 specific routines
 */
static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucByte);
static unsigned8 nvramMkRead(unsigned32 ulOffset);
 
/*
 * STK11C68 specific routines
 */
static void nvramStk11C68Commit();
/*
 * STK11C88 specific routines
 */
static void nvramStk11C88Commit();
 
/*
 * NvRAM hook tables
 */
NVRAM_ENTRY_TABLE nvramDsTable =
{
        nvramDsWrite,
        nvramDsRead,
        nvramCommitStub,
        DS1385_NVSIZE
};
 
NVRAM_ENTRY_TABLE nvramMkTable =
{
        nvramMkWrite,
        nvramMkRead,
        nvramCommitStub,
        MK48T18_NVSIZE
};
 
/*
 * As the STK devicxe is at the same address as the MK device,
 * the MK read/write routines may be used
 */
NVRAM_ENTRY_TABLE nvramStkTable =
{
        nvramMkWrite,
        nvramMkRead,
        nvramStk11C68Commit,
        STK11C68_NVSIZE
};
 
NVRAM_ENTRY_TABLE nvramStk88Table =
{
        nvramMkWrite,
        nvramMkRead,
        nvramStk11C88Commit,
        STK11C88_NVSIZE
};
 
/*
 * Private variables
 */
static PNVRAM_ENTRY_TABLE pNvRAMFunc;
static boolean          bNvRAMChanged=FALSE;
static unsigned32       ulPRePOSAreaLength;
static unsigned32       ulPRePOSAreaOffset;
 
/*
 * Mutual-exclusion semaphore
 */
static rtems_id semNvRAM;
 
/*
 * These routines support the ds1385
 */
static unsigned8 nvramDsRead(unsigned32 ulOffset)
{
        unsigned8 ucTemp;
 
        ucTemp = ulOffset & 0xff;
        outport_byte(DS1385_PORT_BASE, ucTemp);
 
        ucTemp = (ulOffset >> 8) & 0xf;
        outport_byte((DS1385_PORT_BASE + 1) , ucTemp);
 
        inport_byte(DS1385_PORT_BASE+3, ucTemp);
        return(ucTemp);
}
 
static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucData)
{
        unsigned8 ucTemp;
 
        ucTemp = (unsigned8)(ulOffset & 0xff);
        outport_byte(DS1385_PORT_BASE, (unsigned8) ucTemp);
 
        ucTemp = (unsigned8)((ulOffset >> 8) & 0xf);
        outport_byte((DS1385_PORT_BASE + 1) , (unsigned8)ucTemp);
 
        outport_byte((DS1385_PORT_BASE+3), ucData);
}
 
/*
 * These routines support the MK48T18 and STK11C68
 */
static unsigned8 nvramMkRead(unsigned32 ulOffset)
{
        unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE;
 
        return(pNvRAM[ulOffset]);
}
 
static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucData)
{
        unsigned8 *pNvRAM = (unsigned8 *)MK48T18_BASE;
 
        pNvRAM[ulOffset]=ucData;
}
 
/*
 * This routine provides a stub for NvRAM devices which
 * do not require a commit operation
 */
static void nvramCommitStub()
{
}
 
/*
 * This routine triggers a transfer from the NvRAM to the
 * EE array in the STK11C68 device
 */
static void nvramStk11C68Commit()
{
#if 0
        rtems_interval          ticks_per_second;
        rtems_status_code       status;
#endif
 
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        /*
         * Issue Store command
         */
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x0000);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x1555);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x0aaa);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x1fff);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x10f0);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x0f0f);
        EIEIO;
        /*
         * Delay for 10mS to allow store to
         * complete
         */
#if 0
        status = rtems_clock_get(
                RTEMS_CLOCK_GET_TICKS_PER_SECOND,
                &ticks_per_second
        );
 
        status = rtems_task_wake_after(ticks_per_second/100);
#endif
        bNvRAMChanged=FALSE;
 
        rtems_semaphore_release(semNvRAM);
}
 
/*
 * This routine triggers a transfer from the NvRAM to the
 * EE array in the STK11C88 device
 */
static void nvramStk11C88Commit()
{
#if 0
        rtems_interval          ticks_per_second;
        rtems_status_code       status;
#endif
 
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        /*
         * Issue Store command
         */
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x0e38);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x31c7);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x03e0);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x3c1f);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x303f);
        EIEIO;
        (void)pNvRAMFunc->nvramRead(0x0fc0);
        EIEIO;
        /*
         * Delay for 10mS to allow store to
         * complete
         */
#if 0
        status = rtems_clock_get(
                RTEMS_CLOCK_GET_TICKS_PER_SECOND,
                &ticks_per_second
        );
 
        status = rtems_task_wake_after(ticks_per_second/100);
#endif
        bNvRAMChanged=FALSE;
 
        rtems_semaphore_release(semNvRAM);
}
 
/*
 * These are the publically accessable routines
 */
/*
 * This routine returns the size of the NvRAM
 */
unsigned32 SizeNvRAM()
{
        return(ulPRePOSAreaLength);
}
 
/*
 * This routine commits changes to the NvRAM
 */
void CommitNvRAM()
{
        if(bNvRAMChanged)
        {
                (pNvRAMFunc->nvramCommit)();
        }
}
 
/*
 * This routine reads a byte from the NvRAM
 */
rtems_status_code ReadNvRAM8(unsigned32 ulOffset, unsigned8 *pucData)
{
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        *pucData=pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset);
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
/*
 * This routine writes a byte to the NvRAM
 */
rtems_status_code WriteNvRAM8(unsigned32 ulOffset, unsigned8 ucValue)
{
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        pNvRAMFunc->nvramWrite(ulPRePOSAreaOffset+ulOffset, ucValue);
        bNvRAMChanged=TRUE;
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
/*
 * This routine reads a block of bytes from the NvRAM
 */
rtems_status_code ReadNvRAMBlock(
  unsigned32 ulOffset, unsigned8 *pucData, unsigned32 length)
{
        unsigned32 i;
 
        if((ulOffset + length) > ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        for ( i=0 ; i<length ; i++ )
                pucData[i] =
                        pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset+i);
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
/*
 * This routine writes a block of bytes to the NvRAM
 */
rtems_status_code WriteNvRAMBlock(
  unsigned32 ulOffset, unsigned8 *ucValue, unsigned32 length)
{
        unsigned32 i;
 
        if((ulOffset + length) > ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
 
        for ( i=0 ; i<length ; i++ )
                pNvRAMFunc->nvramWrite(
                        ulPRePOSAreaOffset+ulOffset+i, ucValue[i]);
        bNvRAMChanged=TRUE;
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
/*
 * The NVRAM holds data in Big-Endian format
 */
rtems_status_code ReadNvRAM16 (unsigned32 ulOffset, unsigned16 *pusData)
{
        unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
 
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        *pusData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 8) +
                 (pNvRAMFunc->nvramRead(ulTrueOffset + 1));
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
rtems_status_code WriteNvRAM16 (unsigned32 ulOffset, unsigned16 usValue)
{
        unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
 
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (usValue >> 8));
        pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) usValue);
        bNvRAMChanged=TRUE;
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
rtems_status_code ReadNvRAM32 (unsigned32 ulOffset, unsigned32 *pulData)
{
        unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
 
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        *pulData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 24) +
                 (pNvRAMFunc->nvramRead(ulTrueOffset + 1) << 16) +
                 (pNvRAMFunc->nvramRead(ulTrueOffset + 2) << 8) +
                 (pNvRAMFunc->nvramRead(ulTrueOffset + 3));
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
rtems_status_code WriteNvRAM32 (unsigned32 ulOffset, unsigned32 ulValue)
{
        unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;
 
        if(ulOffset>ulPRePOSAreaLength)
        {
                return RTEMS_INVALID_ADDRESS;
        }
        rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
        pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (ulValue >> 24));
        pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) (ulValue >> 16));
        pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (unsigned8) (ulValue >> 8));
        pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (unsigned8) ulValue);
        bNvRAMChanged=TRUE;
        rtems_semaphore_release(semNvRAM);
        return(RTEMS_SUCCESSFUL);
}
 
void
InitializeNvRAM(void)
{
        PHEADER pNvHeader = (PHEADER)0;
        rtems_status_code sc;
        unsigned32 ulLength, ulOffset;
 
        if(ucSystemType==SYS_TYPE_PPC1)
        {
                if(ucBoardRevMaj<5)
                {
                        pNvRAMFunc=&nvramDsTable;
                }
                else
                {
                        pNvRAMFunc=&nvramMkTable;
                }
        }
        else if(ucSystemType==SYS_TYPE_PPC1a)
        {
                pNvRAMFunc=&nvramMkTable;
        }
        else if(ucSystemType==SYS_TYPE_PPC4)
        {
                pNvRAMFunc=&nvramStk88Table;
        }
        else
        {
                pNvRAMFunc=&nvramStkTable;
        }
 
        /*
         * Set up mutex semaphore
         */
        sc = rtems_semaphore_create (
                rtems_build_name ('N', 'V', 'R', 's'),
                1,
                RTEMS_BINARY_SEMAPHORE |
                RTEMS_INHERIT_PRIORITY |
                RTEMS_PRIORITY,
                RTEMS_NO_PRIORITY,
                &semNvRAM);
        if (sc != RTEMS_SUCCESSFUL)
        {
                rtems_fatal_error_occurred (sc);
        }
 
        /*
         * Initially access the whole of NvRAM until we determine where the
         * OS Area is located.
         */
        ulPRePOSAreaLength=0xffffffff;
        ulPRePOSAreaOffset=0;
 
        /*
         * Access the header at the start of NvRAM
         */
        ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaLength), &ulLength);
        ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaAddress), &ulOffset);
 
        /*
         * Now set limits for future accesses
         */
        ulPRePOSAreaLength=ulLength;
        ulPRePOSAreaOffset=ulOffset;
}
 
 

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [nvram/] [nvram.c] - Blame information for rev 30

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* This file contains the NvRAM driver for the PPCn_60x`
3			`*`
4			`* COPYRIGHT (c) 1998 by Radstone Technology`
5			`*`
6			`*`
7			`* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY`
8			`* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE`
9			`* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK`
10			`* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.`
11			`*`
12			`* You are hereby granted permission to use, copy, modify, and distribute`
13			`* this file, provided that this notice, plus the above copyright notice`
14			`* and disclaimer, appears in all copies. Radstone Technology will provide`
15			`* no support for this code.`
16			`*`
17			`*/`
18
19			`#include <bsp.h>`
20			`#include "ds1385.h"`
21			`#include "mk48t18.h"`
22			`#include "stk11c68.h"`
23
24			`/*`
25			`* Private types`
26			`*/`
27			`typedef`
28			`void`
29			`(*PNVRAMWRITE)`
30			`(`
31			`unsigned32 ulOffset,`
32			`unsigned8 ucByte`
33			`);`
34
35			`typedef`
36			`unsigned8`
37			`(*PNVRAMREAD)`
38			`(`
39			`unsigned32 ulOffset`
40			`);`
41
42			`typedef`
43			`void`
44			`(*PNVRAMCOMMIT)`
45			`(`
46			`);`
47
48			`typedef struct _NVRAM_ENTRY_TABLE`
49			`{`
50			`PNVRAMWRITE nvramWrite;`
51			`PNVRAMREAD nvramRead;`
52			`PNVRAMCOMMIT nvramCommit;`
53			`unsigned32 nvramSize;`
54			`} NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE;`
55
56			`/*`
57			`* Private routines`
58			`*/`
59
60			`/*`
61			`* This routine provides a stub for NvRAM devices which`
62			`* do not require a commit operation`
63			`*/`
64			`static void nvramCommitStub();`
65
66			`/*`
67			`* DS1385 specific routines`
68			`*/`
69			`static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucByte);`
70			`static unsigned8 nvramDsRead(unsigned32 ulOffset);`
71
72			`/*`
73			`* MK48T18 specific routines`
74			`*/`
75			`static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucByte);`
76			`static unsigned8 nvramMkRead(unsigned32 ulOffset);`
77
78			`/*`
79			`* STK11C68 specific routines`
80			`*/`
81			`static void nvramStk11C68Commit();`
82			`/*`
83			`* STK11C88 specific routines`
84			`*/`
85			`static void nvramStk11C88Commit();`
86
87			`/*`
88			`* NvRAM hook tables`
89			`*/`
90			`NVRAM_ENTRY_TABLE nvramDsTable =`
91			`{`
92			`nvramDsWrite,`
93			`nvramDsRead,`
94			`nvramCommitStub,`
95			`DS1385_NVSIZE`
96			`};`
97
98			`NVRAM_ENTRY_TABLE nvramMkTable =`
99			`{`
100			`nvramMkWrite,`
101			`nvramMkRead,`
102			`nvramCommitStub,`
103			`MK48T18_NVSIZE`
104			`};`
105
106			`/*`
107			`* As the STK devicxe is at the same address as the MK device,`
108			`* the MK read/write routines may be used`
109			`*/`
110			`NVRAM_ENTRY_TABLE nvramStkTable =`
111			`{`
112			`nvramMkWrite,`
113			`nvramMkRead,`
114			`nvramStk11C68Commit,`
115			`STK11C68_NVSIZE`
116			`};`
117
118			`NVRAM_ENTRY_TABLE nvramStk88Table =`
119			`{`
120			`nvramMkWrite,`
121			`nvramMkRead,`
122			`nvramStk11C88Commit,`
123			`STK11C88_NVSIZE`
124			`};`
125
126			`/*`
127			`* Private variables`
128			`*/`
129			`static PNVRAM_ENTRY_TABLE pNvRAMFunc;`
130			`static boolean bNvRAMChanged=FALSE;`
131			`static unsigned32 ulPRePOSAreaLength;`
132			`static unsigned32 ulPRePOSAreaOffset;`
133
134			`/*`
135			`* Mutual-exclusion semaphore`
136			`*/`
137			`static rtems_id semNvRAM;`
138
139			`/*`
140			`* These routines support the ds1385`
141			`*/`
142			`static unsigned8 nvramDsRead(unsigned32 ulOffset)`
143			`{`
144			`unsigned8 ucTemp;`
145
146			`ucTemp = ulOffset & 0xff;`
147			`outport_byte(DS1385_PORT_BASE, ucTemp);`
148
149			`ucTemp = (ulOffset >> 8) & 0xf;`
150			`outport_byte((DS1385_PORT_BASE + 1) , ucTemp);`
151
152			`inport_byte(DS1385_PORT_BASE+3, ucTemp);`
153			`return(ucTemp);`
154			`}`
155
156			`static void nvramDsWrite(unsigned32 ulOffset, unsigned8 ucData)`
157			`{`
158			`unsigned8 ucTemp;`
159
160			`ucTemp = (unsigned8)(ulOffset & 0xff);`
161			`outport_byte(DS1385_PORT_BASE, (unsigned8) ucTemp);`
162
163			`ucTemp = (unsigned8)((ulOffset >> 8) & 0xf);`
164			`outport_byte((DS1385_PORT_BASE + 1) , (unsigned8)ucTemp);`
165
166			`outport_byte((DS1385_PORT_BASE+3), ucData);`
167			`}`
168
169			`/*`
170			`* These routines support the MK48T18 and STK11C68`
171			`*/`
172			`static unsigned8 nvramMkRead(unsigned32 ulOffset)`
173			`{`
174			`unsigned8 pNvRAM = (unsigned8 )MK48T18_BASE;`
175
176			`return(pNvRAM[ulOffset]);`
177			`}`
178
179			`static void nvramMkWrite(unsigned32 ulOffset, unsigned8 ucData)`
180			`{`
181			`unsigned8 pNvRAM = (unsigned8 )MK48T18_BASE;`
182
183			`pNvRAM[ulOffset]=ucData;`
184			`}`
185
186			`/*`
187			`* This routine provides a stub for NvRAM devices which`
188			`* do not require a commit operation`
189			`*/`
190			`static void nvramCommitStub()`
191			`{`
192			`}`
193
194			`/*`
195			`* This routine triggers a transfer from the NvRAM to the`
196			`* EE array in the STK11C68 device`
197			`*/`
198			`static void nvramStk11C68Commit()`
199			`{`
200			`#if 0`
201			`rtems_interval ticks_per_second;`
202			`rtems_status_code status;`
203			`#endif`
204
205			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
206			`/*`
207			`* Issue Store command`
208			`*/`
209			`EIEIO;`
210			`(void)pNvRAMFunc->nvramRead(0x0000);`
211			`EIEIO;`
212			`(void)pNvRAMFunc->nvramRead(0x1555);`
213			`EIEIO;`
214			`(void)pNvRAMFunc->nvramRead(0x0aaa);`
215			`EIEIO;`
216			`(void)pNvRAMFunc->nvramRead(0x1fff);`
217			`EIEIO;`
218			`(void)pNvRAMFunc->nvramRead(0x10f0);`
219			`EIEIO;`
220			`(void)pNvRAMFunc->nvramRead(0x0f0f);`
221			`EIEIO;`
222			`/*`
223			`* Delay for 10mS to allow store to`
224			`* complete`
225			`*/`
226			`#if 0`
227			`status = rtems_clock_get(`
228			`RTEMS_CLOCK_GET_TICKS_PER_SECOND,`
229			`&ticks_per_second`
230			`);`
231
232			`status = rtems_task_wake_after(ticks_per_second/100);`
233			`#endif`
234			`bNvRAMChanged=FALSE;`
235
236			`rtems_semaphore_release(semNvRAM);`
237			`}`
238
239			`/*`
240			`* This routine triggers a transfer from the NvRAM to the`
241			`* EE array in the STK11C88 device`
242			`*/`
243			`static void nvramStk11C88Commit()`
244			`{`
245			`#if 0`
246			`rtems_interval ticks_per_second;`
247			`rtems_status_code status;`
248			`#endif`
249
250			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
251			`/*`
252			`* Issue Store command`
253			`*/`
254			`EIEIO;`
255			`(void)pNvRAMFunc->nvramRead(0x0e38);`
256			`EIEIO;`
257			`(void)pNvRAMFunc->nvramRead(0x31c7);`
258			`EIEIO;`
259			`(void)pNvRAMFunc->nvramRead(0x03e0);`
260			`EIEIO;`
261			`(void)pNvRAMFunc->nvramRead(0x3c1f);`
262			`EIEIO;`
263			`(void)pNvRAMFunc->nvramRead(0x303f);`
264			`EIEIO;`
265			`(void)pNvRAMFunc->nvramRead(0x0fc0);`
266			`EIEIO;`
267			`/*`
268			`* Delay for 10mS to allow store to`
269			`* complete`
270			`*/`
271			`#if 0`
272			`status = rtems_clock_get(`
273			`RTEMS_CLOCK_GET_TICKS_PER_SECOND,`
274			`&ticks_per_second`
275			`);`
276
277			`status = rtems_task_wake_after(ticks_per_second/100);`
278			`#endif`
279			`bNvRAMChanged=FALSE;`
280
281			`rtems_semaphore_release(semNvRAM);`
282			`}`
283
284			`/*`
285			`* These are the publically accessable routines`
286			`*/`
287			`/*`
288			`* This routine returns the size of the NvRAM`
289			`*/`
290			`unsigned32 SizeNvRAM()`
291			`{`
292			`return(ulPRePOSAreaLength);`
293			`}`
294
295			`/*`
296			`* This routine commits changes to the NvRAM`
297			`*/`
298			`void CommitNvRAM()`
299			`{`
300			`if(bNvRAMChanged)`
301			`{`
302			`(pNvRAMFunc->nvramCommit)();`
303			`}`
304			`}`
305
306			`/*`
307			`* This routine reads a byte from the NvRAM`
308			`*/`
309			`rtems_status_code ReadNvRAM8(unsigned32 ulOffset, unsigned8 *pucData)`
310			`{`
311			`if(ulOffset>ulPRePOSAreaLength)`
312			`{`
313			`return RTEMS_INVALID_ADDRESS;`
314			`}`
315			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
316			`*pucData=pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset);`
317			`rtems_semaphore_release(semNvRAM);`
318			`return(RTEMS_SUCCESSFUL);`
319			`}`
320
321			`/*`
322			`* This routine writes a byte to the NvRAM`
323			`*/`
324			`rtems_status_code WriteNvRAM8(unsigned32 ulOffset, unsigned8 ucValue)`
325			`{`
326			`if(ulOffset>ulPRePOSAreaLength)`
327			`{`
328			`return RTEMS_INVALID_ADDRESS;`
329			`}`
330			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
331			`pNvRAMFunc->nvramWrite(ulPRePOSAreaOffset+ulOffset, ucValue);`
332			`bNvRAMChanged=TRUE;`
333			`rtems_semaphore_release(semNvRAM);`
334			`return(RTEMS_SUCCESSFUL);`
335			`}`
336
337			`/*`
338			`* This routine reads a block of bytes from the NvRAM`
339			`*/`
340			`rtems_status_code ReadNvRAMBlock(`
341			`unsigned32 ulOffset, unsigned8 *pucData, unsigned32 length)`
342			`{`
343			`unsigned32 i;`
344
345			`if((ulOffset + length) > ulPRePOSAreaLength)`
346			`{`
347			`return RTEMS_INVALID_ADDRESS;`
348			`}`
349			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
350			`for ( i=0 ; i<length ; i++ )`
351			`pucData[i] =`
352			`pNvRAMFunc->nvramRead(ulPRePOSAreaOffset+ulOffset+i);`
353			`rtems_semaphore_release(semNvRAM);`
354			`return(RTEMS_SUCCESSFUL);`
355			`}`
356
357			`/*`
358			`* This routine writes a block of bytes to the NvRAM`
359			`*/`
360			`rtems_status_code WriteNvRAMBlock(`
361			`unsigned32 ulOffset, unsigned8 *ucValue, unsigned32 length)`
362			`{`
363			`unsigned32 i;`
364
365			`if((ulOffset + length) > ulPRePOSAreaLength)`
366			`{`
367			`return RTEMS_INVALID_ADDRESS;`
368			`}`
369			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
370
371			`for ( i=0 ; i<length ; i++ )`
372			`pNvRAMFunc->nvramWrite(`
373			`ulPRePOSAreaOffset+ulOffset+i, ucValue[i]);`
374			`bNvRAMChanged=TRUE;`
375			`rtems_semaphore_release(semNvRAM);`
376			`return(RTEMS_SUCCESSFUL);`
377			`}`
378
379			`/*`
380			`* The NVRAM holds data in Big-Endian format`
381			`*/`
382			`rtems_status_code ReadNvRAM16 (unsigned32 ulOffset, unsigned16 *pusData)`
383			`{`
384			`unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;`
385
386			`if(ulOffset>ulPRePOSAreaLength)`
387			`{`
388			`return RTEMS_INVALID_ADDRESS;`
389			`}`
390			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
391			`*pusData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 8) +`
392			`(pNvRAMFunc->nvramRead(ulTrueOffset + 1));`
393			`rtems_semaphore_release(semNvRAM);`
394			`return(RTEMS_SUCCESSFUL);`
395			`}`
396
397			`rtems_status_code WriteNvRAM16 (unsigned32 ulOffset, unsigned16 usValue)`
398			`{`
399			`unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;`
400
401			`if(ulOffset>ulPRePOSAreaLength)`
402			`{`
403			`return RTEMS_INVALID_ADDRESS;`
404			`}`
405			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
406			`pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (usValue >> 8));`
407			`pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) usValue);`
408			`bNvRAMChanged=TRUE;`
409			`rtems_semaphore_release(semNvRAM);`
410			`return(RTEMS_SUCCESSFUL);`
411			`}`
412
413			`rtems_status_code ReadNvRAM32 (unsigned32 ulOffset, unsigned32 *pulData)`
414			`{`
415			`unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;`
416
417			`if(ulOffset>ulPRePOSAreaLength)`
418			`{`
419			`return RTEMS_INVALID_ADDRESS;`
420			`}`
421			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
422			`*pulData=(pNvRAMFunc->nvramRead(ulTrueOffset) << 24) +`
423			`(pNvRAMFunc->nvramRead(ulTrueOffset + 1) << 16) +`
424			`(pNvRAMFunc->nvramRead(ulTrueOffset + 2) << 8) +`
425			`(pNvRAMFunc->nvramRead(ulTrueOffset + 3));`
426			`rtems_semaphore_release(semNvRAM);`
427			`return(RTEMS_SUCCESSFUL);`
428			`}`
429
430			`rtems_status_code WriteNvRAM32 (unsigned32 ulOffset, unsigned32 ulValue)`
431			`{`
432			`unsigned32 ulTrueOffset=ulPRePOSAreaOffset+ulOffset;`
433
434			`if(ulOffset>ulPRePOSAreaLength)`
435			`{`
436			`return RTEMS_INVALID_ADDRESS;`
437			`}`
438			`rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT);`
439			`pNvRAMFunc->nvramWrite(ulTrueOffset, (unsigned8) (ulValue >> 24));`
440			`pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (unsigned8) (ulValue >> 16));`
441			`pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (unsigned8) (ulValue >> 8));`
442			`pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (unsigned8) ulValue);`
443			`bNvRAMChanged=TRUE;`
444			`rtems_semaphore_release(semNvRAM);`
445			`return(RTEMS_SUCCESSFUL);`
446			`}`
447
448			`void`
449			`InitializeNvRAM(void)`
450			`{`
451			`PHEADER pNvHeader = (PHEADER)0;`
452			`rtems_status_code sc;`
453			`unsigned32 ulLength, ulOffset;`
454
455			`if(ucSystemType==SYS_TYPE_PPC1)`
456			`{`
457			`if(ucBoardRevMaj<5)`
458			`{`
459			`pNvRAMFunc=&nvramDsTable;`
460			`}`
461			`else`
462			`{`
463			`pNvRAMFunc=&nvramMkTable;`
464			`}`
465			`}`
466			`else if(ucSystemType==SYS_TYPE_PPC1a)`
467			`{`
468			`pNvRAMFunc=&nvramMkTable;`
469			`}`
470			`else if(ucSystemType==SYS_TYPE_PPC4)`
471			`{`
472			`pNvRAMFunc=&nvramStk88Table;`
473			`}`
474			`else`
475			`{`
476			`pNvRAMFunc=&nvramStkTable;`
477			`}`
478
479			`/*`
480			`* Set up mutex semaphore`
481			`*/`
482			`sc = rtems_semaphore_create (`
483			`rtems_build_name ('N', 'V', 'R', 's'),`
484			`1,`
485			`RTEMS_BINARY_SEMAPHORE \|`
486			`RTEMS_INHERIT_PRIORITY \|`
487			`RTEMS_PRIORITY,`
488			`RTEMS_NO_PRIORITY,`
489			`&semNvRAM);`
490			`if (sc != RTEMS_SUCCESSFUL)`
491			`{`
492			`rtems_fatal_error_occurred (sc);`
493			`}`
494
495			`/*`
496			`* Initially access the whole of NvRAM until we determine where the`
497			`* OS Area is located.`
498			`*/`
499			`ulPRePOSAreaLength=0xffffffff;`
500			`ulPRePOSAreaOffset=0;`
501
502			`/*`
503			`* Access the header at the start of NvRAM`
504			`*/`
505			`ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaLength), &ulLength);`
506			`ReadNvRAM32((unsigned32)(&pNvHeader->OSAreaAddress), &ulOffset);`
507
508			`/*`
509			`* Now set limits for future accesses`
510			`*/`
511			`ulPRePOSAreaLength=ulLength;`
512			`ulPRePOSAreaOffset=ulOffset;`
513			`}`
514
515