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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [pci/] [pci.c] - Blame information for rev 389

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/*
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 *  COPYRIGHT (c) 1998 by Radstone Technology
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 *
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 *
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 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
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 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
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 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
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 *
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 * You are hereby granted permission to use, copy, modify, and distribute
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 * this file, provided that this notice, plus the above copyright notice
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 * and disclaimer, appears in all copies. Radstone Technology will provide
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 * no support for this code.
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 *
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 */
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#include <bsp.h>
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#include <pci.h>
18 
 
19 
/* SCE 97/4/9
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 *
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 * Use PCI configuration space access mechanism 1
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 *
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 * This is the preferred access mechanism and must be used when accessing
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 * bridged PCI busses.
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 *
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 * The address to be written to the PCI_CONFIG_ADDRESS port is constructed
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 * thus (the representation below is little endian):
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 *
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 *  31  30   24 23        16 15        11 10        8 7          2 1   0
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 *  ----------------------------------------------------------------------
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 * | 1 | Resvd | Bus Number | Dev Number | Fn Number | Reg Number | 0 | 0 |
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 *  ----------------------------------------------------------------------
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 *
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 * On bus 0, the first 'real' device is at Device number 11, the Eagle being
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 * device 0. On all other busses, device numbering starts at 0.
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 */
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/*
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 * Normal PCI device numbering on busses other than 0 is such that
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 * that the first device (0) is attached to AD16, second (1) to AD17 etc.
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 */
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#define CONFIG_ADDRESS(Bus, Device, Function, Offset) \
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    (0x80000000 | (Bus<<16) | \
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    ((Device+(((Bus==0)&&(Device>0)) ? 10 : 0))<<11) | \
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    (Function<<8) | \
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    (Offset&~0x03))
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#define BYTE_LANE_OFFSET(Offset) ((Offset)&0x3)
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48 
/*
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 * Private data
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 */
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static unsigned8 ucMaxPCIBus;
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53 
/*
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 * Public routines
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 */
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rtems_status_code PCIConfigWrite8(
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        unsigned8 ucBusNumber,
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        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned8 ucValue
62 
)
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{
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        ISR_Level Irql;
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66 
        /*
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         * Ensure that accesses to the addr/data ports are indivisible
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         */
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        _ISR_Disable(Irql);
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71 
        /*
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         * Write to the configuration space address register
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         */
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        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
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         * Write to the configuration space data register with the appropriate
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         * offset
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         */
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        outport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), ucValue);
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83 
         _ISR_Enable(Irql);
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85 
        return(RTEMS_SUCCESSFUL);
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}
87 
 
88 
rtems_status_code PCIConfigWrite16(
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        unsigned8 ucBusNumber,
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        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned16 usValue
94 
)
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{
96 
        ISR_Level Irql;
97 
 
98 
        /*
99 
         * Ensure that accesses to the addr/data ports are indivisible
100 
         */
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        _ISR_Disable(Irql);
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103 
        /*
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         * Write to the configuration space address register
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         */
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        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
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         * Write to the configuration space data register with the appropriate
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         * offset
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         */
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        outport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), usValue);
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115 
        _ISR_Enable(Irql);
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117 
        return(RTEMS_SUCCESSFUL);
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}
119 
 
120 
rtems_status_code PCIConfigWrite32(
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        unsigned8 ucBusNumber,
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        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned32 ulValue
126 
)
127 
{
128 
        ISR_Level Irql;
129 
 
130 
        /*
131 
         * Ensure that accesses to the addr/data ports are indivisible
132 
         */
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        _ISR_Disable(Irql);
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135 
        /*
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         * Write to the configuration space address register
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         */
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        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
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         * Write to the configuration space data register with the appropriate
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         * offset
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         */
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        outport_32(PCI_CONFIG_DATA, ulValue);
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        _ISR_Enable(Irql);
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149 
        return(RTEMS_SUCCESSFUL);
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}
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152 
rtems_status_code PCIConfigRead8(
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        unsigned8 ucBusNumber,
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        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned8 *pucValue
158 
)
159 
{
160 
        ISR_Level Irql;
161 
 
162 
        /*
163 
         * Ensure that accesses to the addr/data ports are indivisible
164 
         */
165 
        _ISR_Disable(Irql);
166 
 
167 
        /*
168 
         * Write to the configuration space address register
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         */
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        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
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         * Read from the configuration space data register with the appropriate
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         * offset
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         */
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        inport_byte(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pucValue);
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179 
        _ISR_Enable(Irql);
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        return(RTEMS_SUCCESSFUL);
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}
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rtems_status_code PCIConfigRead16(
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        unsigned8 ucBusNumber,
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        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned16 *pusValue
190 
)
191 
{
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        ISR_Level Irql;
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194 
        /*
195 
         * Ensure that accesses to the addr/data ports are indivisible
196 
         */
197 
        _ISR_Disable(Irql);
198 
 
199 
        /*
200 
         * Write to the configuration space address register
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         */
202 
        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
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         * Read from the configuration space data register with the appropriate
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         * offset
208 
         */
209 
        inport_16(PCI_CONFIG_DATA+BYTE_LANE_OFFSET(ucOffset), *pusValue);
210 
 
211 
        _ISR_Enable(Irql);
212 
 
213 
        return(RTEMS_SUCCESSFUL);
214 
}
215 
 
216 
rtems_status_code PCIConfigRead32(
217 
        unsigned8 ucBusNumber,
218 
        unsigned8 ucSlotNumber,
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        unsigned8 ucFunctionNumber,
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        unsigned8 ucOffset,
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        unsigned32 *pulValue
222 
)
223 
{
224 
        ISR_Level Irql;
225 
 
226 
        /*
227 
         * Ensure that accesses to the addr/data ports are indivisible
228 
         */
229 
        _ISR_Disable(Irql);
230 
 
231 
        /*
232 
         * Write to the configuration space address register
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         */
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        outport_32(PCI_CONFIG_ADDR,
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                   CONFIG_ADDRESS(ucBusNumber, ucSlotNumber,
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                                  ucFunctionNumber, ucOffset));
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        /*
238 
         * Read from the configuration space data register with the appropriate
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         * offset
240 
         */
241 
        inport_32(PCI_CONFIG_DATA, *pulValue);
242 
 
243 
        _ISR_Enable(Irql);
244 
 
245 
        return(RTEMS_SUCCESSFUL);
246 
}
247 
 
248 
/*
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 * This routine determines the maximum bus number in the system
250 
 */
251 
void InitializePCI()
252 
{
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        unsigned8 ucSlotNumber, ucFnNumber, ucNumFuncs;
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        unsigned8 ucHeader;
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        unsigned8 ucBaseClass, ucSubClass, ucMaxSubordinate;
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        unsigned32 ulDeviceID;
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258 
        /*
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         * Scan PCI bus 0 looking for PCI-PCI bridges
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         */
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        for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++)
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        {
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                (void)PCIConfigRead32(0,
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                                      ucSlotNumber,
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                                      0,
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                                      PCI_CONFIG_VENDOR_LOW,
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                                      &ulDeviceID);
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                if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
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                {
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                        /*
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                         * This slot is empty
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                         */
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                        continue;
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                }
275 
                (void)PCIConfigRead8(0,
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                                     ucSlotNumber,
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                                     0,
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                                     PCI_CONFIG_HEADER_TYPE,
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                                     &ucHeader);
280 
                if(ucHeader&PCI_MULTI_FUNCTION)
281 
                {
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                        ucNumFuncs=PCI_MAX_FUNCTIONS;
283 
                }
284 
                else
285 
                {
286 
                        ucNumFuncs=1;
287 
                }
288 
                for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++)
289 
                {
290 
                        (void)PCIConfigRead32(0,
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                                              ucSlotNumber,
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                                              ucFnNumber,
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                                              PCI_CONFIG_VENDOR_LOW,
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                                              &ulDeviceID);
295 
                        if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
296 
                        {
297 
                                /*
298 
                                 * This slot/function is empty
299 
                                 */
300 
                                continue;
301 
                        }
302 
 
303 
                        /*
304 
                         * This slot/function has a device fitted.
305 
                         */
306 
                        (void)PCIConfigRead8(0,
307 
                                             ucSlotNumber,
308 
                                             ucFnNumber,
309 
                                             PCI_CONFIG_CLASS_CODE_U,
310 
                                             &ucBaseClass);
311 
                        (void)PCIConfigRead8(0,
312 
                                             ucSlotNumber,
313 
                                             ucFnNumber,
314 
                                             PCI_CONFIG_CLASS_CODE_M,
315 
                                             &ucSubClass);
316 
                        if((ucBaseClass==PCI_BASE_CLASS_BRIDGE) &&
317 
                           (ucSubClass==PCI_SUB_CLASS_BRIDGE_PCI))
318 
                        {
319 
                                /*
320 
                                 * We have found a PCI-PCI bridge
321 
                                 */
322 
                                (void)PCIConfigRead8(0,
323 
                                                     ucSlotNumber,
324 
                                                     ucFnNumber,
325 
                                                     PCI_BRIDGE_SUBORDINATE_BUS,
326 
                                                     &ucMaxSubordinate);
327 
                                if(ucMaxSubordinate>ucMaxPCIBus)
328 
                                {
329 
                                        ucMaxPCIBus=ucMaxSubordinate;
330 
                                }
331 
                        }
332 
                }
333 
        }
334 
}
335 
 
336 
/*
337 
 * Return the number of PCI busses in the system
338 
 */
339 
unsigned8 BusCountPCI()
340 
{
341 
        return(ucMaxPCIBus+1);
342 
}

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