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/*
 * This is based on the mvme-crt0.S file from libgloss/rs6000.
 * crt0.S -- startup file for PowerPC systems.
 *
 * (c) 1998, Radstone Technology plc.
 *
 *
 * This is an unpublished work the copyright  in  which   vests
 * in  Radstone Technology plc.  All rights reserved.
 *
 * The information contained herein is the property of Radstone
 * Technology  plc.  and  is  supplied  without  liability  for
 * errors or omissions and no part may be reproduced,  used  or
 * disclosed except as authorized by contract or  other written
 * permission.     The    copyright    and    the     foregoing
 * restriction   on  reproduction, use and disclosure extend to
 * all  the   media   in   which   this  information   may   be
 * embodied.
 *
 * Copyright (c) 1995 Cygnus Support
 *
 * The authors hereby grant permission to use, copy, modify, distribute,
 * and license this software and its documentation for any purpose, provided
 * that existing copyright notices are retained in all copies and that this
 * notice is included verbatim in any distributions. No written agreement,
 * license, or royalty fee is required for any of the authorized uses.
 * Modifications to this software may be copyrighted by their authors
 * and need not follow the licensing terms described here, provided that
 * the new terms are clearly indicated on the first page of each file where
 * they apply.
 *
 *  $Id: start.S,v 1.2 2001-09-27 12:00:54 chris Exp $
 */
#include 
#include "ppc-asm.h"
#include "bsp.h"
 
        .file   "start.s"
 
        .extern FUNC_NAME(atexit)
        .globl  FUNC_NAME(__atexit)
        .section ".sdata","aw"
        .align  2
FUNC_NAME(__atexit):                    /* tell C's eabi-ctor's we have an atexit function */
        .long   FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
 
        .section ".fixup","aw"
        .align  2
        .long   FUNC_NAME(__atexit)
 
        .text
        .globl  _start
        .type   _start,@function
_start:
        /* Set MSR */
        /*
         * Enable data and instruction address translation and floating point
         */
        li      r3,MSR_IR | MSR_DR | MSR_FP
        mtmsr   r3
 
        /*
         * The caches are already flushed by the firmware so just enable
         */
        mfspr   r3,HID0
#if PPC_USE_DATA_CACHE
        /*
         * Enable data and instruction cache
         */
        ori     r3,r3 ,H0_60X_ICE | H0_60X_DCE
#else
        /*
         * Enable instruction cache only
         */
        ori     r3,r3 ,H0_60X_ICE
#endif
        mtspr   HID0,r3
 
        /* clear bss */
        lis     r6,__bss_start@h
        ori     r6,r6,__bss_start@l
        lis     r7,__bss_end@h
        ori     r7,r7,__bss_end@l
 
        cmplw   1,r6,r7
        bc      4,4,.Lbss_done
 
        subf    r8,r6,r7                /* number of bytes to zero */
        srwi    r9,r8,2                 /* number of words to zero */
        mtctr   r9
        li      r0,0                    /* zero to clear memory */
        addi    r6,r6,-4                /* adjust so we can use stwu */
.Lbss_loop:
        stwu    r0,4(r6)                /* zero bss */
        bdnz    .Lbss_loop
 
.Lbss_done:
 
        /* clear sbss */
        lis     r6,__sbss_start@h
        ori     r6,r6,__sbss_start@l
        lis     r7,__sbss_end@h
        ori     r7,r7,__sbss_end@l
 
        cmplw   1,r6,r7
        bc      4,4,.Lsbss_done
 
        subf    r8,r6,r7                /* number of bytes to zero */
        srwi    r9,r8,2                 /* number of words to zero */
        mtctr   r9
        li      r0,0                    /* zero to clear memory */
        addi    r6,r6,-4                /* adjust so we can use stwu */
.Lsbss_loop:
        stwu    r0,4(r6)                /* zero sbss */
        bdnz    .Lsbss_loop
 
.Lsbss_done:
 
        lis     sp,__stack@h
        ori     sp,sp,__stack@l
 
        /* set up initial stack frame */
        addi    sp,sp,-4                /* make sure we don't overwrite debug mem */
        lis     r0,0
        stw     r0,0(sp)                /* clear back chain */
        stwu    sp,-56(sp)              /* push another stack frame */
 
        li      r3, 0                   /* argc */
        li      r4, 0                   /* argv */
        li      r5, 0                   /* environp */
 
        /* Let her rip */
        bl      FUNC_NAME(boot_card)
 
        /*
         * This should never get reached
         */
        /*
         * Return MSR to its reset state
         */
        li      r3,0
        mtmsr   r3
        isync
 
        /*
         * Call reset entry point
         */
        lis     r3,0xfff0
        ori     r3,r3,0x100
        mtlr    r3
        blr
.Lstart:
        .size   _start,.Lstart-_start

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* This is based on the mvme-crt0.S file from libgloss/rs6000.`
3			`* crt0.S -- startup file for PowerPC systems.`
4			`*`
5			`* (c) 1998, Radstone Technology plc.`
6			`*`
7			`*`
8			`* This is an unpublished work the copyright in which vests`
9			`* in Radstone Technology plc. All rights reserved.`
10			`*`
11			`* The information contained herein is the property of Radstone`
12			`* Technology plc. and is supplied without liability for`
13			`* errors or omissions and no part may be reproduced, used or`
14			`* disclosed except as authorized by contract or other written`
15			`* permission. The copyright and the foregoing`
16			`* restriction on reproduction, use and disclosure extend to`
17			`* all the media in which this information may be`
18			`* embodied.`
19			`*`
20			`* Copyright (c) 1995 Cygnus Support`
21			`*`
22			`* The authors hereby grant permission to use, copy, modify, distribute,`
23			`* and license this software and its documentation for any purpose, provided`
24			`* that existing copyright notices are retained in all copies and that this`
25			`* notice is included verbatim in any distributions. No written agreement,`
26			`* license, or royalty fee is required for any of the authorized uses.`
27			`* Modifications to this software may be copyrighted by their authors`
28			`* and need not follow the licensing terms described here, provided that`
29			`* the new terms are clearly indicated on the first page of each file where`
30			`* they apply.`
31			`*`
32			`* $Id: start.S,v 1.2 2001-09-27 12:00:54 chris Exp $`
33			`*/`
34			`#include`
35			`#include "ppc-asm.h"`
36			`#include "bsp.h"`
37
38			`.file "start.s"`
39
40			`.extern FUNC_NAME(atexit)`
41			`.globl FUNC_NAME(__atexit)`
42			`.section ".sdata","aw"`
43			`.align 2`
44			`FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */`
45			`.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */`
46
47			`.section ".fixup","aw"`
48			`.align 2`
49			`.long FUNC_NAME(__atexit)`
50
51			`.text`
52			`.globl _start`
53			`.type _start,@function`
54			`_start:`
55			`/* Set MSR */`
56			`/*`
57			`* Enable data and instruction address translation and floating point`
58			`*/`
59			`li r3,MSR_IR \| MSR_DR \| MSR_FP`
60			`mtmsr r3`
61
62			`/*`
63			`* The caches are already flushed by the firmware so just enable`
64			`*/`
65			`mfspr r3,HID0`
66			`#if PPC_USE_DATA_CACHE`
67			`/*`
68			`* Enable data and instruction cache`
69			`*/`
70			`ori r3,r3 ,H0_60X_ICE \| H0_60X_DCE`
71			`#else`
72			`/*`
73			`* Enable instruction cache only`
74			`*/`
75			`ori r3,r3 ,H0_60X_ICE`
76			`#endif`
77			`mtspr HID0,r3`
78
79			`/* clear bss */`
80			`lis r6,__bss_start@h`
81			`ori r6,r6,__bss_start@l`
82			`lis r7,__bss_end@h`
83			`ori r7,r7,__bss_end@l`
84
85			`cmplw 1,r6,r7`
86			`bc 4,4,.Lbss_done`
87
88			`subf r8,r6,r7 /* number of bytes to zero */`
89			`srwi r9,r8,2 /* number of words to zero */`
90			`mtctr r9`
91			`li r0,0 /* zero to clear memory */`
92			`addi r6,r6,-4 /* adjust so we can use stwu */`
93			`.Lbss_loop:`
94			`stwu r0,4(r6) /* zero bss */`
95			`bdnz .Lbss_loop`
96
97			`.Lbss_done:`
98
99			`/* clear sbss */`
100			`lis r6,__sbss_start@h`
101			`ori r6,r6,__sbss_start@l`
102			`lis r7,__sbss_end@h`
103			`ori r7,r7,__sbss_end@l`
104
105			`cmplw 1,r6,r7`
106			`bc 4,4,.Lsbss_done`
107
108			`subf r8,r6,r7 /* number of bytes to zero */`
109			`srwi r9,r8,2 /* number of words to zero */`
110			`mtctr r9`
111			`li r0,0 /* zero to clear memory */`
112			`addi r6,r6,-4 /* adjust so we can use stwu */`
113			`.Lsbss_loop:`
114			`stwu r0,4(r6) /* zero sbss */`
115			`bdnz .Lsbss_loop`
116
117			`.Lsbss_done:`
118
119			`lis sp,__stack@h`
120			`ori sp,sp,__stack@l`
121
122			`/* set up initial stack frame */`
123			`addi sp,sp,-4 /* make sure we don't overwrite debug mem */`
124			`lis r0,0`
125			`stw r0,0(sp) /* clear back chain */`
126			`stwu sp,-56(sp) /* push another stack frame */`
127
128			`li r3, 0 /* argc */`
129			`li r4, 0 /* argv */`
130			`li r5, 0 /* environp */`
131
132			`/* Let her rip */`
133			`bl FUNC_NAME(boot_card)`
134
135			`/*`
136			`* This should never get reached`
137			`*/`
138			`/*`
139			`* Return MSR to its reset state`
140			`*/`
141			`li r3,0`
142			`mtmsr r3`
143			`isync`
144
145			`/*`
146			`* Call reset entry point`
147			`*/`
148			`lis r3,0xfff0`
149			`ori r3,r3,0x100`
150			`mtlr r3`
151			`blr`
152			`.Lstart:`
153			`.size _start,.Lstart-_start`

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [start/] [start.S] - Blame information for rev 30