OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [startup/] [swap.c] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  COPYRIGHT (c) 1998 by Radstone Technology
3
 *
4
 *
5
 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
6
 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
7
 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
8
 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
9
 *
10
 * You are hereby granted permission to use, copy, modify, and distribute
11
 * this file, provided that this notice, plus the above copyright notice
12
 * and disclaimer, appears in all copies. Radstone Technology will provide
13
 * no support for this code.
14
 *
15
 */
16
 
17
#include <rtems.h>
18
 
19
/*
20
 *  JRS - February 20, 1998
21
 *
22
 *  There is a swap32 in each port.  So this should be removed.
23
 *
24
 *  Adding a swap16 to the port would be useful.
25
 *
26
 *  The end of all this would be to remove this file.
27
 */
28
 
29
inline unsigned int Swap32(
30
        unsigned32 ulValue
31
)
32
{
33
        unsigned32 ulSwapped;
34
 
35
        asm volatile(
36
                "rlwimi %0,%1,8,24,31;"
37
                "rlwimi %0,%1,24,16,23;"
38
                "rlwimi %0,%1,8,8,15;"
39
                "rlwimi %0,%1,24,0,7;" :
40
 
41
                "=&r" ((ulSwapped)) :
42
                "r" ((ulValue))
43
        );
44
 
45
        return( ulSwapped );
46
}
47
 
48
inline unsigned int Swap16(
49
        unsigned16 usValue
50
)
51
{
52
        unsigned16 usSwapped;
53
 
54
        asm volatile(
55
                "rlwimi %0,%1,24,24,31;"
56
                "rlwimi %0,%1,8,16,23;" :
57
 
58
                "=&r" ((usSwapped)) :
59
                "r" ((usValue))
60
        );
61
 
62
        return( usSwapped );
63
}
64
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.