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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [universe/] [universe.c] - Blame information for rev 30

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/*
 *  COPYRIGHT (c) 1998 by Radstone Technology
 *
 *
 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
 *
 * You are hereby granted permission to use, copy, modify, and distribute
 * this file, provided that this notice, plus the above copyright notice
 * and disclaimer, appears in all copies. Radstone Technology will provide
 * no support for this code.
 *
 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
 *  On-Line Applications Research Corporation (OAR).
 *  All rights assigned to U.S. Government, 1994.
 *
 *  This material may be reproduced by or for the U.S. Government pursuant
 *  to the copyright license under the clause at DFARS 252.227-7013.  This
 *  notice must appear in all copies of this file and its derivatives.
 *
 * $ld:
 */
 
#include <rtems.h>
#include <assert.h>
#include <stdio.h>
 
#include <bsp.h>
#include <pci.h>
 
/********************************************************************
 ********************************************************************
 *********                                                  *********
 *********                  Prototypes                      *********
 *********                                                  *********
 ********************************************************************
 ********************************************************************/
 
typedef struct {
  rtems_unsigned32 PCI_ID;                 /* Offset 0x0000 */
  rtems_unsigned32 PCI_CSR;                /* Offset 0x0004 */
  rtems_unsigned32 PCI_CLASS;              /* Offset 0x0008 */
  rtems_unsigned32 PCI_MISC0;              /* Offset 0x000C */
  rtems_unsigned32 PCI_BS;                 /* Offset 0x0010 */
  rtems_unsigned32 Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */
  rtems_unsigned32 PCI_MISC1;              /* Offset 0x003C */
  rtems_unsigned32 Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */
  rtems_unsigned32 LSI0_CTL;               /* Offset 0x0100 */
  rtems_unsigned32 LSI0_BS;                /* Offset 0x0104 */
  rtems_unsigned32 LSI0_BD;                /* Offset 0x0108 */
  rtems_unsigned32 LSI0_TO;                /* Offset 0x010C */
  rtems_unsigned32 Buf_Offset_0x0110;         /* Offset 0x0110 */
  rtems_unsigned32 LSI1_CTL;               /* Offset 0x0114 */
  rtems_unsigned32 LSI1_BS;                /* Offset 0x0118 */
  rtems_unsigned32 LSI1_BD;                /* Offset 0x011C */
  rtems_unsigned32 LSI1_TO;                /* Offset 0x0120 */
  rtems_unsigned32 Buf_Offset_0x0124;         /* Offset 0x0124 */
  rtems_unsigned32 LSI2_CTL;               /* Offset 0x0128 */
  rtems_unsigned32 LSI2_BS;                /* Offset 0x012C */
  rtems_unsigned32 LSI2_BD;                /* Offset 0x0130 */
  rtems_unsigned32 LSI2_TO;                /* Offset 0x0134 */
  rtems_unsigned32 Buf_Offset_0x0138;         /* Offset 0x0138 */
  rtems_unsigned32 LSI3_CTL;               /* Offset 0x013C */
  rtems_unsigned32 LSI3_BS;                /* Offset 0x0140 */
  rtems_unsigned32 LSI3_BD;                /* Offset 0x0144 */
  rtems_unsigned32 LSI3_TO;                /* Offset 0x0148 */
  rtems_unsigned32 Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */
  rtems_unsigned32 SCYC_CTL;               /* Offset 0x0170 */
  rtems_unsigned32 SCYC_ADDR;              /* Offset 0x0174 */
  rtems_unsigned32 SCYC_EN;                /* Offset 0x0178 */
  rtems_unsigned32 SCYC_CMP;               /* Offset 0x017C */
  rtems_unsigned32 SCYC_SWP;               /* Offset 0x0180 */
  rtems_unsigned32 LMISC;                  /* Offset 0x0184 */
  rtems_unsigned32 SLSI;                   /* Offset 0x0188 */
  rtems_unsigned32 L_CMDERR;               /* Offset 0x018C */
  rtems_unsigned32 LAERR;                  /* Offset 0x0190 */
  rtems_unsigned32 Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */
  rtems_unsigned32 DCTL;                   /* Offset 0x0200 */
  rtems_unsigned32 DTBC;                   /* Offset 0x0204 */
  rtems_unsigned32 DLA;                    /* Offset 0x0208 */
  rtems_unsigned32 Buf_Offset_0x020C;         /* Offset 0x020C */
  rtems_unsigned32 DVA;                    /* Offset 0x0210 */
  rtems_unsigned32 Buf_Offset_0x0214;         /* Offset 0x0214 */
  rtems_unsigned32 DCPP;                   /* Offset 0x0218 */
  rtems_unsigned32 Buf_Offset_0x021C;         /* Offset 0x021C */
  rtems_unsigned32 DGCS;                   /* Offset 0x0220 */
  rtems_unsigned32 D_LLUE;                 /* Offset 0x0224 */
  rtems_unsigned32 Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */
  rtems_unsigned32 LINT_EN;                /* Offset 0x0300 */
  rtems_unsigned32 LINT_STAT;              /* Offset 0x0304 */
  rtems_unsigned32 LINT_MAP0;              /* Offset 0x0308 */
  rtems_unsigned32 LINT_MAP1;              /* Offset 0x030C */
  rtems_unsigned32 VINT_EN;                /* Offset 0x0310 */
  rtems_unsigned32 VINT_STAT;              /* Offset 0x0314 */
  rtems_unsigned32 VINT_MAP0;              /* Offset 0x0318 */
  rtems_unsigned32 VINT_MAP1;              /* Offset 0x031C */
  rtems_unsigned32 STATID;                 /* Offset 0x0320 */
  rtems_unsigned32 V1_STATID;              /* Offset 0x0324 */
  rtems_unsigned32 V2_STATID;              /* Offset 0x0328 */
  rtems_unsigned32 V3_STATID;              /* Offset 0x032C */
  rtems_unsigned32 V4_STATID;              /* Offset 0x0330 */
  rtems_unsigned32 V5_STATID;              /* Offset 0x0334 */
  rtems_unsigned32 V6_STATID;              /* Offset 0x0338 */
  rtems_unsigned32 V7_STATID;              /* Offset 0x033C */
  rtems_unsigned32 Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */
  rtems_unsigned32 MAST_CTL;               /* Offset 0x0400 */
  rtems_unsigned32 MISC_CTL;               /* Offset 0x0404 */
  rtems_unsigned32 MISC_STAT;              /* Offset 0x0408 */
  rtems_unsigned32 USER_AM;                /* Offset 0x040C */
  rtems_unsigned32 Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */
  rtems_unsigned32 VSI0_CTL;               /* Offset 0x0F00 */
  rtems_unsigned32 VSI0_BS;                /* Offset 0x0F04 */
  rtems_unsigned32 VSI0_BD;                /* Offset 0x0F08 */
  rtems_unsigned32 VSI0_TO;                /* Offset 0x0F0C */
  rtems_unsigned32 Buf_Offset_0x0f10;         /* Offset 0x0F10 */
  rtems_unsigned32 VSI1_CTL;               /* Offset 0x0F14 */
  rtems_unsigned32 VSI1_BS;                /* Offset 0x0F18 */
  rtems_unsigned32 VSI1_BD;                /* Offset 0x0F1C */
  rtems_unsigned32 VSI1_TO;                /* Offset 0x0F20 */
  rtems_unsigned32 Buf_Offset_0x0F24;         /* Offset 0x0F24 */
  rtems_unsigned32 VSI2_CTL;               /* Offset 0x0F28 */
  rtems_unsigned32 VSI2_BS;                /* Offset 0x0F2C */
  rtems_unsigned32 VSI2_BD;                /* Offset 0x0F30 */
  rtems_unsigned32 VSI2_TO;                /* Offset 0x0F34 */
  rtems_unsigned32 Buf_Offset_0x0F38;         /* Offset 0x0F38 */
  rtems_unsigned32 VSI3_CTL;               /* Offset 0x0F3C */
  rtems_unsigned32 VSI3_BS;                /* Offset 0x0F40 */
  rtems_unsigned32 VSI3_BD;                /* Offset 0x0F44 */
  rtems_unsigned32 VSI3_TO;                /* Offset 0x0F48 */
  rtems_unsigned32 Buf_Offset_0x0F4C[ 0x9 ];  /* Offset 0x0F4C */
  rtems_unsigned32 VRAI_CTL;               /* Offset 0x0F70 */
  rtems_unsigned32 VRAI_BS;                /* Offset 0x0F74 */
  rtems_unsigned32 Buf_Offset_0x0F78[ 0x2 ];  /* Offset 0x0F78 */
  rtems_unsigned32 VCSR_CTL;               /* Offset 0x0F80 */
  rtems_unsigned32 VCSR_TO;                /* Offset 0x0F84 */
  rtems_unsigned32 V_AMERR;                /* Offset 0x0F88 */
  rtems_unsigned32 VAERR;                  /* Offset 0x0F8C */
  rtems_unsigned32 Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */
  rtems_unsigned32 VCSR_CLR;               /* Offset 0x0FF4 */
  rtems_unsigned32 VCSR_SET;               /* Offset 0x0FF8 */
  rtems_unsigned32 VCSR_BS;                /* Offset 0x0FFC */
} Universe_Memory;
 
volatile Universe_Memory *UNIVERSE;
 
/*
 * PCI_bus_write
 */
void PCI_bus_write(
  volatile rtems_unsigned32 * _addr,                  /* IN */
  rtems_unsigned32 _data                              /* IN */
)
{
  outport_32(_addr, _data);
}
 
rtems_unsigned32 PCI_bus_read(
  volatile rtems_unsigned32 *  _addr                  /* IN */
)
{
  rtems_unsigned32 data;
 
  inport_32(_addr, data);
  return data;
}
 
/********************************************************************
 ********************************************************************
 *********                                                  *********
 *********                                                  *********
 *********                                                  *********
 ********************************************************************
 ********************************************************************/
 
/*
 * Initializes the UNIVERSE chip.  This routine is called automatically
 * by the boot code.  This routine should be called by user code only if
 * a complete PPCn_60x VME initialization is required.
 */
 
void InitializeUniverse()
{
  rtems_unsigned32 pci_id;
  rtems_unsigned32 universe_temp_value;
 
  /*
   * Verify the UNIVERSE CHIP ID
   */
   (void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id);
 
   /*
    * compare to known ID
    */
   if (pci_id != 0x000010e3 ){
     DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: ");
     rtems_fatal_error_occurred( 0x603e0bad );
   }
 
   (void)PCIConfigRead32(0,4,0,PCI_CONFIG_BAR_0, &universe_temp_value);
   UNIVERSE = (Universe_Memory *)(universe_temp_value & ~PCI_ADDRESS_IO_SPACE);
 
   /*
    * Set the UNIVERSE PCI Configuration Space Control and Status Register to
    * medium speed device, Target Back to Back Capable, Master Enable, Target
    * Memory Enable and Target IO Enable
    */
   PCIConfigWrite32(0,4,0,PCI_CONFIG_COMMAND, PCI_ENABLE_IO_SPACE |
                                              PCI_ENABLE_MEMORY_SPACE |
                                              PCI_ENABLE_BUS_MASTER);
 
   /*
    * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
    */
   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
 
#if 0
   /*
    * Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register.
    */
   PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 );
 
   /*
    * Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register.
    */
   PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 );
 
   /*
    * VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO
    * register. Map the VME base address 0x4000000 to local memory address 0x0
    */
   PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 );
 
   /*
    * Set the VMEbus Slave Image 0 Control register with write posted,
    * read prefetch and AM code set for program, data, supervisor and user mode
    */
   PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 );
#endif
 
   /*
    * Set the VMEbus Master Control register with retry forever, 256 bytes
    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
    * aligned burst size and PCI bus number to be zero
    */
   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
 
   /*
    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
    */
 
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
 
 
#if 0
   /*
    * Set the PCI Slave Image 0 Control register with posted write enable,
    * 32 bit data width, A32 VMEbus address base, AM code to be data,
    * none-privilleged, single and BLT cycles on VME bus with PCI
    * bus memory space.
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 );
    */
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
 
   /*
    * Set the PCI Slave Image 0 Base Address to be
    * 0x0 on LSI0_BS register.
    */
   PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 );
 
   /*
    * Set the PCI Slave Image 0 Bound Address to be
    * 0xFFFFF000 on VSI0_BD register.
    */
   PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 );
 
   /*
    * Set the PCI Slave Image 0 Translation Offset to be
    * 0x0 on VSI0_TO register.
    * Note: If the actual VME address is bigger than 0x40000000, we need
    *   to set the PCI Slave Image 0 Translation Offset = 0x40000000
    *   register.
    *   i.e. if actual VME ADRR = 0x50000000, then we
    *     need to subtract it by 0x40000000 and set
    *      the LSI0_T0 register to be 0x40000000 and then
    *     perform a PCI data access by adding 0xC0000000 to
    *     0x10000000 -- which is came form the result of
    *     (0x50000000 - 0x40000000).
    */
   PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 );
#endif
 
   /*
    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
    * BI-Mode VMEbus accesses can be made.
    */
 
   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
 
   if (universe_temp_value & 0x100000)
     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
}
 
/*
 * Set the slave VME base address to the specified base address.
 * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
 *       Slave Image 0 registers.
 */
void set_vme_base_address (
  rtems_unsigned32 base_address
)
{
  volatile rtems_unsigned32 temp;
 
  /*
   * Calculate the current size of the Slave VME image 0
   */
  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
          ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
 
  /*
   * Set the VMEbus Slave Image 0 Base Address to be
   * the specifed base address on VSI0_BS register.
   */
   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
 
  /*
   * Update the VMEbus Slave Image 0 Bound Address.
   */
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
 
  /*
   * Update the VMEbus Slave Image 0 Translation Offset
   */
  temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
  PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
}
 
/*
 * Gets the VME base address
 */
rtems_unsigned32 get_vme_base_address ()
{
  volatile rtems_unsigned32 temp;
 
  temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
  temp &= 0xFFFFF000;
  return (temp);
}
 
rtems_unsigned32 get_vme_slave_size()
{
  volatile rtems_unsigned32 temp;
  temp  =  PCI_bus_read( &UNIVERSE->VSI0_BD);
  temp &= 0xFFFFF000;
  temp  = temp - get_vme_base_address ();
  return temp;
}
 
/*
 * Set the size of the VME slave image
 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
 */
void set_vme_slave_size (rtems_unsigned32 size)
{
  volatile rtems_unsigned32 temp;
 
  if (size<0)
    size = 0;
 
  if (size > 0x17FFFFF)
    size = 0x17FFFFF;
 
  /*
   * Read the VME slave image base address
   */
  temp = get_vme_base_address ();
 
  /*
   * Update the VMEbus Slave Image 0 Bound Address.
   */
  temp = temp + (size & 0xFFFFF000);
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
}
 
#if 0
/* XXXXX */
/*
 * Returns the 16 bit location specified by vme_ptr, which must be a
 * pointer to VME D16 space
 */
rtems_unsigned16 get_vme(
  rtems_unsigned16 *vme_ptr
)
{
  rtems_unsigned16 result;
 
  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF)
  {
    /*
     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
     */
    if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000)
         PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
 
    result = (*(rtems_unsigned16 *)(
               ((rtems_unsigned32)vme_ptr - 0x3EFFF000)+
                PPCN_60X_PCI_MEM_BASE) );
   }
   else
     result = (*(rtems_unsigned16 *)
                ((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE));
 
   return result;
}
 
/*
 * Stores the 16 bit word at the location specified by vme_ptr, which must
 * be a pointer to VME D16 space
 */
void put_vme(
  rtems_unsigned16 *vme_ptr,
  rtems_unsigned16 value
)
{
 
  if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) {
    /*
     * LSI0_TO register to 0x3EFFF000 if it had not been updated already
     */
     if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000)
       PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );
 
    *(rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) +
                            PPCN_60X_PCI_MEM_BASE) = value;
   }
   else
      *(rtems_unsigned16 *)((rtems_unsigned32)vme_ptr +
                             PPCN_60X_PCI_MEM_BASE) = value;
}
#endif
 

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [universe/] [universe.c] - Blame information for rev 30

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* COPYRIGHT (c) 1998 by Radstone Technology`
3			`*`
4			`*`
5			`* THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY`
6			`* KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE`
7			`* IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK`
8			`* AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.`
9			`*`
10			`* You are hereby granted permission to use, copy, modify, and distribute`
11			`* this file, provided that this notice, plus the above copyright notice`
12			`* and disclaimer, appears in all copies. Radstone Technology will provide`
13			`* no support for this code.`
14			`*`
15			`* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.`
16			`* On-Line Applications Research Corporation (OAR).`
17			`* All rights assigned to U.S. Government, 1994.`
18			`*`
19			`* This material may be reproduced by or for the U.S. Government pursuant`
20			`* to the copyright license under the clause at DFARS 252.227-7013. This`
21			`* notice must appear in all copies of this file and its derivatives.`
22			`*`
23			`* $ld:`
24			`*/`
25
26			`#include <rtems.h>`
27			`#include <assert.h>`
28			`#include <stdio.h>`
29
30			`#include <bsp.h>`
31			`#include <pci.h>`
32
33			`/********************************************************************`
34			`********************************************************************`
35			`******* *******`
36			`******* Prototypes *******`
37			`******* *******`
38			`********************************************************************`
39			`********************************************************************/`
40
41			`typedef struct {`
42			`rtems_unsigned32 PCI_ID; /* Offset 0x0000 */`
43			`rtems_unsigned32 PCI_CSR; /* Offset 0x0004 */`
44			`rtems_unsigned32 PCI_CLASS; /* Offset 0x0008 */`
45			`rtems_unsigned32 PCI_MISC0; /* Offset 0x000C */`
46			`rtems_unsigned32 PCI_BS; /* Offset 0x0010 */`
47			`rtems_unsigned32 Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */`
48			`rtems_unsigned32 PCI_MISC1; /* Offset 0x003C */`
49			`rtems_unsigned32 Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */`
50			`rtems_unsigned32 LSI0_CTL; /* Offset 0x0100 */`
51			`rtems_unsigned32 LSI0_BS; /* Offset 0x0104 */`
52			`rtems_unsigned32 LSI0_BD; /* Offset 0x0108 */`
53			`rtems_unsigned32 LSI0_TO; /* Offset 0x010C */`
54			`rtems_unsigned32 Buf_Offset_0x0110; /* Offset 0x0110 */`
55			`rtems_unsigned32 LSI1_CTL; /* Offset 0x0114 */`
56			`rtems_unsigned32 LSI1_BS; /* Offset 0x0118 */`
57			`rtems_unsigned32 LSI1_BD; /* Offset 0x011C */`
58			`rtems_unsigned32 LSI1_TO; /* Offset 0x0120 */`
59			`rtems_unsigned32 Buf_Offset_0x0124; /* Offset 0x0124 */`
60			`rtems_unsigned32 LSI2_CTL; /* Offset 0x0128 */`
61			`rtems_unsigned32 LSI2_BS; /* Offset 0x012C */`
62			`rtems_unsigned32 LSI2_BD; /* Offset 0x0130 */`
63			`rtems_unsigned32 LSI2_TO; /* Offset 0x0134 */`
64			`rtems_unsigned32 Buf_Offset_0x0138; /* Offset 0x0138 */`
65			`rtems_unsigned32 LSI3_CTL; /* Offset 0x013C */`
66			`rtems_unsigned32 LSI3_BS; /* Offset 0x0140 */`
67			`rtems_unsigned32 LSI3_BD; /* Offset 0x0144 */`
68			`rtems_unsigned32 LSI3_TO; /* Offset 0x0148 */`
69			`rtems_unsigned32 Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */`
70			`rtems_unsigned32 SCYC_CTL; /* Offset 0x0170 */`
71			`rtems_unsigned32 SCYC_ADDR; /* Offset 0x0174 */`
72			`rtems_unsigned32 SCYC_EN; /* Offset 0x0178 */`
73			`rtems_unsigned32 SCYC_CMP; /* Offset 0x017C */`
74			`rtems_unsigned32 SCYC_SWP; /* Offset 0x0180 */`
75			`rtems_unsigned32 LMISC; /* Offset 0x0184 */`
76			`rtems_unsigned32 SLSI; /* Offset 0x0188 */`
77			`rtems_unsigned32 L_CMDERR; /* Offset 0x018C */`
78			`rtems_unsigned32 LAERR; /* Offset 0x0190 */`
79			`rtems_unsigned32 Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */`
80			`rtems_unsigned32 DCTL; /* Offset 0x0200 */`
81			`rtems_unsigned32 DTBC; /* Offset 0x0204 */`
82			`rtems_unsigned32 DLA; /* Offset 0x0208 */`
83			`rtems_unsigned32 Buf_Offset_0x020C; /* Offset 0x020C */`
84			`rtems_unsigned32 DVA; /* Offset 0x0210 */`
85			`rtems_unsigned32 Buf_Offset_0x0214; /* Offset 0x0214 */`
86			`rtems_unsigned32 DCPP; /* Offset 0x0218 */`
87			`rtems_unsigned32 Buf_Offset_0x021C; /* Offset 0x021C */`
88			`rtems_unsigned32 DGCS; /* Offset 0x0220 */`
89			`rtems_unsigned32 D_LLUE; /* Offset 0x0224 */`
90			`rtems_unsigned32 Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */`
91			`rtems_unsigned32 LINT_EN; /* Offset 0x0300 */`
92			`rtems_unsigned32 LINT_STAT; /* Offset 0x0304 */`
93			`rtems_unsigned32 LINT_MAP0; /* Offset 0x0308 */`
94			`rtems_unsigned32 LINT_MAP1; /* Offset 0x030C */`
95			`rtems_unsigned32 VINT_EN; /* Offset 0x0310 */`
96			`rtems_unsigned32 VINT_STAT; /* Offset 0x0314 */`
97			`rtems_unsigned32 VINT_MAP0; /* Offset 0x0318 */`
98			`rtems_unsigned32 VINT_MAP1; /* Offset 0x031C */`
99			`rtems_unsigned32 STATID; /* Offset 0x0320 */`
100			`rtems_unsigned32 V1_STATID; /* Offset 0x0324 */`
101			`rtems_unsigned32 V2_STATID; /* Offset 0x0328 */`
102			`rtems_unsigned32 V3_STATID; /* Offset 0x032C */`
103			`rtems_unsigned32 V4_STATID; /* Offset 0x0330 */`
104			`rtems_unsigned32 V5_STATID; /* Offset 0x0334 */`
105			`rtems_unsigned32 V6_STATID; /* Offset 0x0338 */`
106			`rtems_unsigned32 V7_STATID; /* Offset 0x033C */`
107			`rtems_unsigned32 Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */`
108			`rtems_unsigned32 MAST_CTL; /* Offset 0x0400 */`
109			`rtems_unsigned32 MISC_CTL; /* Offset 0x0404 */`
110			`rtems_unsigned32 MISC_STAT; /* Offset 0x0408 */`
111			`rtems_unsigned32 USER_AM; /* Offset 0x040C */`
112			`rtems_unsigned32 Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */`
113			`rtems_unsigned32 VSI0_CTL; /* Offset 0x0F00 */`
114			`rtems_unsigned32 VSI0_BS; /* Offset 0x0F04 */`
115			`rtems_unsigned32 VSI0_BD; /* Offset 0x0F08 */`
116			`rtems_unsigned32 VSI0_TO; /* Offset 0x0F0C */`
117			`rtems_unsigned32 Buf_Offset_0x0f10; /* Offset 0x0F10 */`
118			`rtems_unsigned32 VSI1_CTL; /* Offset 0x0F14 */`
119			`rtems_unsigned32 VSI1_BS; /* Offset 0x0F18 */`
120			`rtems_unsigned32 VSI1_BD; /* Offset 0x0F1C */`
121			`rtems_unsigned32 VSI1_TO; /* Offset 0x0F20 */`
122			`rtems_unsigned32 Buf_Offset_0x0F24; /* Offset 0x0F24 */`
123			`rtems_unsigned32 VSI2_CTL; /* Offset 0x0F28 */`
124			`rtems_unsigned32 VSI2_BS; /* Offset 0x0F2C */`
125			`rtems_unsigned32 VSI2_BD; /* Offset 0x0F30 */`
126			`rtems_unsigned32 VSI2_TO; /* Offset 0x0F34 */`
127			`rtems_unsigned32 Buf_Offset_0x0F38; /* Offset 0x0F38 */`
128			`rtems_unsigned32 VSI3_CTL; /* Offset 0x0F3C */`
129			`rtems_unsigned32 VSI3_BS; /* Offset 0x0F40 */`
130			`rtems_unsigned32 VSI3_BD; /* Offset 0x0F44 */`
131			`rtems_unsigned32 VSI3_TO; /* Offset 0x0F48 */`
132			`rtems_unsigned32 Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */`
133			`rtems_unsigned32 VRAI_CTL; /* Offset 0x0F70 */`
134			`rtems_unsigned32 VRAI_BS; /* Offset 0x0F74 */`
135			`rtems_unsigned32 Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */`
136			`rtems_unsigned32 VCSR_CTL; /* Offset 0x0F80 */`
137			`rtems_unsigned32 VCSR_TO; /* Offset 0x0F84 */`
138			`rtems_unsigned32 V_AMERR; /* Offset 0x0F88 */`
139			`rtems_unsigned32 VAERR; /* Offset 0x0F8C */`
140			`rtems_unsigned32 Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */`
141			`rtems_unsigned32 VCSR_CLR; /* Offset 0x0FF4 */`
142			`rtems_unsigned32 VCSR_SET; /* Offset 0x0FF8 */`
143			`rtems_unsigned32 VCSR_BS; /* Offset 0x0FFC */`
144			`} Universe_Memory;`
145
146			`volatile Universe_Memory *UNIVERSE;`
147
148			`/*`
149			`* PCI_bus_write`
150			`*/`
151			`void PCI_bus_write(`
152			`volatile rtems_unsigned32 * _addr, /* IN */`
153			`rtems_unsigned32 _data /* IN */`
154			`)`
155			`{`
156			`outport_32(_addr, _data);`
157			`}`
158
159			`rtems_unsigned32 PCI_bus_read(`
160			`volatile rtems_unsigned32 * _addr /* IN */`
161			`)`
162			`{`
163			`rtems_unsigned32 data;`
164
165			`inport_32(_addr, data);`
166			`return data;`
167			`}`
168
169			`/********************************************************************`
170			`********************************************************************`
171			`******* *******`
172			`******* *******`
173			`******* *******`
174			`********************************************************************`
175			`********************************************************************/`
176
177			`/*`
178			`* Initializes the UNIVERSE chip. This routine is called automatically`
179			`* by the boot code. This routine should be called by user code only if`
180			`* a complete PPCn_60x VME initialization is required.`
181			`*/`
182
183			`void InitializeUniverse()`
184			`{`
185			`rtems_unsigned32 pci_id;`
186			`rtems_unsigned32 universe_temp_value;`
187
188			`/*`
189			`* Verify the UNIVERSE CHIP ID`
190			`*/`
191			`(void)PCIConfigRead32(0,4,0,PCI_CONFIG_VENDOR_LOW, &pci_id);`
192
193			`/*`
194			`* compare to known ID`
195			`*/`
196			`if (pci_id != 0x000010e3 ){`
197			`DEBUG_puts ("Invalid PPCN_60X_UNIVERSE_CHIP_ID: ");`
198			`rtems_fatal_error_occurred( 0x603e0bad );`
199			`}`
200
201			`(void)PCIConfigRead32(0,4,0,PCI_CONFIG_BAR_0, &universe_temp_value);`
202			`UNIVERSE = (Universe_Memory *)(universe_temp_value & ~PCI_ADDRESS_IO_SPACE);`
203
204			`/*`
205			`* Set the UNIVERSE PCI Configuration Space Control and Status Register to`
206			`* medium speed device, Target Back to Back Capable, Master Enable, Target`
207			`* Memory Enable and Target IO Enable`
208			`*/`
209			`PCIConfigWrite32(0,4,0,PCI_CONFIG_COMMAND, PCI_ENABLE_IO_SPACE \|`
210			`PCI_ENABLE_MEMORY_SPACE \|`
211			`PCI_ENABLE_BUS_MASTER);`
212
213			`/*`
214			`* Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register`
215			`*/`
216			`PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );`
217
218			`#if 0`
219			`/*`
220			`* Set VMEbus Slave Image 0 Base Address to 0x04000000 on VSI0_BS register.`
221			`*/`
222			`PCI_bus_write( &UNIVERSE->VSI0_BS, 0x04000000 );`
223
224			`/*`
225			`* Set VMEbus Slave Image 0 Bound Address to 0x05000000 on VSI0_BD register.`
226			`*/`
227			`PCI_bus_write( &UNIVERSE->VSI0_BD, 0x05000000 );`
228
229			`/*`
230			`* VMEbus Slave Image 0 Translation Offset to 0x7C000000 on VSI0_TO`
231			`* register. Map the VME base address 0x4000000 to local memory address 0x0`
232			`*/`
233			`PCI_bus_write( &UNIVERSE->VSI0_TO, 0x7C000000 );`
234
235			`/*`
236			`* Set the VMEbus Slave Image 0 Control register with write posted,`
237			`* read prefetch and AM code set for program, data, supervisor and user mode`
238			`*/`
239			`PCI_bus_write( &UNIVERSE->VSI0_CTL, 0xE0F20000 );`
240			`#endif`
241
242			`/*`
243			`* Set the VMEbus Master Control register with retry forever, 256 bytes`
244			`* posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes`
245			`* aligned burst size and PCI bus number to be zero`
246			`*/`
247			`PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );`
248
249			`/*`
250			`* VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data`
251			`* width, A32 VMEbus Address Space, AM code to be data, none-privilleged,`
252			`* single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable`
253			`PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );`
254			`*/`
255
256			`PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );`
257			`PCI_bus_write( &UNIVERSE->LSI0_BS, 0x04000000 );`
258			`PCI_bus_write( &UNIVERSE->LSI0_BD, 0x05000000 );`
259			`PCI_bus_write( &UNIVERSE->LSI0_TO, 0x7C000000 );`
260
261
262			`#if 0`
263			`/*`
264			`* Set the PCI Slave Image 0 Control register with posted write enable,`
265			`* 32 bit data width, A32 VMEbus address base, AM code to be data,`
266			`* none-privilleged, single and BLT cycles on VME bus with PCI`
267			`* bus memory space.`
268			`PCI_bus_write( &UNIVERSE->LSI0_CTL, 0xC0820100 );`
269			`*/`
270			`PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );`
271
272			`/*`
273			`* Set the PCI Slave Image 0 Base Address to be`
274			`* 0x0 on LSI0_BS register.`
275			`*/`
276			`PCI_bus_write( &UNIVERSE->LSI0_BS, 0x00FF0000 );`
277
278			`/*`
279			`* Set the PCI Slave Image 0 Bound Address to be`
280			`* 0xFFFFF000 on VSI0_BD register.`
281			`*/`
282			`PCI_bus_write( &UNIVERSE->LSI0_BD, 0x00FFF000 );`
283
284			`/*`
285			`* Set the PCI Slave Image 0 Translation Offset to be`
286			`* 0x0 on VSI0_TO register.`
287			`* Note: If the actual VME address is bigger than 0x40000000, we need`
288			`* to set the PCI Slave Image 0 Translation Offset = 0x40000000`
289			`* register.`
290			`* i.e. if actual VME ADRR = 0x50000000, then we`
291			`* need to subtract it by 0x40000000 and set`
292			`* the LSI0_T0 register to be 0x40000000 and then`
293			`* perform a PCI data access by adding 0xC0000000 to`
294			`* 0x10000000 -- which is came form the result of`
295			`* (0x50000000 - 0x40000000).`
296			`*/`
297			`PCI_bus_write( &UNIVERSE->LSI0_TO, 0x0 );`
298			`#endif`
299
300			`/*`
301			`* Remove the Universe from VMEbus BI-Mode (bus-isolation). Once out of`
302			`* BI-Mode VMEbus accesses can be made.`
303			`*/`
304
305			`universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );`
306
307			`if (universe_temp_value & 0x100000)`
308			`PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value \| ~0xFF0FFFFF));`
309			`}`
310
311			`/*`
312			`* Set the slave VME base address to the specified base address.`
313			`* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus`
314			`* Slave Image 0 registers.`
315			`*/`
316			`void set_vme_base_address (`
317			`rtems_unsigned32 base_address`
318			`)`
319			`{`
320			`volatile rtems_unsigned32 temp;`
321
322			`/*`
323			`* Calculate the current size of the Slave VME image 0`
324			`*/`
325			`temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -`
326			`( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);`
327
328			`/*`
329			`* Set the VMEbus Slave Image 0 Base Address to be`
330			`* the specifed base address on VSI0_BS register.`
331			`*/`
332			`PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );`
333
334			`/*`
335			`* Update the VMEbus Slave Image 0 Bound Address.`
336			`*/`
337			`PCI_bus_write( &UNIVERSE->VSI0_BD, temp );`
338
339			`/*`
340			`* Update the VMEbus Slave Image 0 Translation Offset`
341			`*/`
342			`temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;`
343			`PCI_bus_write( &UNIVERSE->VSI0_TO, temp );`
344			`}`
345
346			`/*`
347			`* Gets the VME base address`
348			`*/`
349			`rtems_unsigned32 get_vme_base_address ()`
350			`{`
351			`volatile rtems_unsigned32 temp;`
352
353			`temp = PCI_bus_read( &UNIVERSE->VSI0_BS );`
354			`temp &= 0xFFFFF000;`
355			`return (temp);`
356			`}`
357
358			`rtems_unsigned32 get_vme_slave_size()`
359			`{`
360			`volatile rtems_unsigned32 temp;`
361			`temp = PCI_bus_read( &UNIVERSE->VSI0_BD);`
362			`temp &= 0xFFFFF000;`
363			`temp = temp - get_vme_base_address ();`
364			`return temp;`
365			`}`
366
367			`/*`
368			`* Set the size of the VME slave image`
369			`* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)`
370			`*/`
371			`void set_vme_slave_size (rtems_unsigned32 size)`
372			`{`
373			`volatile rtems_unsigned32 temp;`
374
375			`if (size<0)`
376			`size = 0;`
377
378			`if (size > 0x17FFFFF)`
379			`size = 0x17FFFFF;`
380
381			`/*`
382			`* Read the VME slave image base address`
383			`*/`
384			`temp = get_vme_base_address ();`
385
386			`/*`
387			`* Update the VMEbus Slave Image 0 Bound Address.`
388			`*/`
389			`temp = temp + (size & 0xFFFFF000);`
390			`PCI_bus_write( &UNIVERSE->VSI0_BD, temp );`
391			`}`
392
393			`#if 0`
394			`/* XXXXX */`
395			`/*`
396			`* Returns the 16 bit location specified by vme_ptr, which must be a`
397			`* pointer to VME D16 space`
398			`*/`
399			`rtems_unsigned16 get_vme(`
400			`rtems_unsigned16 *vme_ptr`
401			`)`
402			`{`
403			`rtems_unsigned16 result;`
404
405			`if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF)`
406			`{`
407			`/*`
408			`* LSI0_TO register to 0x3EFFF000 if it had not been updated already`
409			`*/`
410			`if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000)`
411			`PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );`
412
413			`result = ((rtems_unsigned16 )(`
414			`((rtems_unsigned32)vme_ptr - 0x3EFFF000)+`
415			`PPCN_60X_PCI_MEM_BASE) );`
416			`}`
417			`else`
418			`result = ((rtems_unsigned16 )`
419			`((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE));`
420
421			`return result;`
422			`}`
423
424			`/*`
425			`* Stores the 16 bit word at the location specified by vme_ptr, which must`
426			`* be a pointer to VME D16 space`
427			`*/`
428			`void put_vme(`
429			`rtems_unsigned16 *vme_ptr,`
430			`rtems_unsigned16 value`
431			`)`
432			`{`
433
434			`if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) {`
435			`/*`
436			`* LSI0_TO register to 0x3EFFF000 if it had not been updated already`
437			`*/`
438			`if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000)`
439			`PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 );`
440
441			`(rtems_unsigned16 ) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) +`
442			`PPCN_60X_PCI_MEM_BASE) = value;`
443			`}`
444			`else`
445			`(rtems_unsigned16 )((rtems_unsigned32)vme_ptr +`
446			`PPCN_60X_PCI_MEM_BASE) = value;`
447			`}`
448			`#endif`
449