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/*
 * (c) 1998, Radstone Technology plc.
 *
 *
 * This is an unpublished work the copyright  in  which   vests
 * in  Radstone Technology plc.  All rights reserved.
 *
 * The information contained herein is the property of Radstone
 * Technology  plc.  and  is  supplied  without  liability  for
 * errors or omissions and no part may be reproduced,  used  or
 * disclosed except as authorized by contract or  other written
 * permission.     The    copyright    and    the     foregoing
 * restriction   on  reproduction, use and disclosure extend to
 * all  the   media   in   which   this  information   may   be
 * embodied.
 *
 */
/*  vectors.s   1.1 - 95/12/04
 *
 *  This file contains the assembly code for the PowerPC
 *  interrupt veneers for RTEMS.
 *
 */
 
/*
 *  The issue with this file is getting it loaded at the right place.
 *  The first vector MUST be at address 0x????0100.
 *  How this is achieved is dependant on the tool chain.
 *
 *  However the basic mechanism for ELF assemblers is to create a
 *  section called ".vectors", which will be loaded to an address
 *  between 0x????0000 and 0x????0100 (inclusive) via a link script.
 *
 *  The basic mechanism for XCOFF assemblers is to place it in the
 *  normal text section, and arrange for this file to be located
 *  at an appropriate position on the linker command line.
 *
 *  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
 *  offset from 0x????0000 to the first location in the file.  This
 *  will usually be 0x0000 or 0x0100.
 *
 *  $Id: vectors.S,v 1.2 2001-09-27 12:01:01 chris Exp $
 */
 
#include "asm.h"
#include "bsp.h"
 
#ifndef PPC_VECTOR_FILE_BASE
#error "PPC_VECTOR_FILE_BASE is not defined."
#endif
 
    .set    IP_LINK, 0
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
    .set    IP_0, (IP_LINK + 56)
#else
    .set    IP_0, (IP_LINK + 8)
#endif
    .set    IP_2, (IP_0 + 4)
 
    .set    IP_3, (IP_2 + 4)
    .set    IP_4, (IP_3 + 4)
    .set    IP_5, (IP_4 + 4)
    .set    IP_6, (IP_5 + 4)
 
    .set    IP_7, (IP_6 + 4)
    .set    IP_8, (IP_7 + 4)
    .set    IP_9, (IP_8 + 4)
    .set    IP_10, (IP_9 + 4)
 
    .set    IP_11, (IP_10 + 4)
    .set    IP_12, (IP_11 + 4)
    .set    IP_13, (IP_12 + 4)
    .set    IP_28, (IP_13 + 4)
 
    .set    IP_29, (IP_28 + 4)
    .set    IP_30, (IP_29 + 4)
    .set    IP_31, (IP_30 + 4)
    .set    IP_CR, (IP_31 + 4)
 
    .set    IP_CTR, (IP_CR + 4)
    .set    IP_XER, (IP_CTR + 4)
    .set    IP_LR, (IP_XER + 4)
    .set    IP_PC, (IP_LR + 4)
 
    .set    IP_MSR, (IP_PC + 4)
 
    .set    IP_END, (IP_MSR + 16)
 
        /* Where this file will be loaded */
        .set    file_base, PPC_VECTOR_FILE_BASE
 
        /* Vector offsets                        */
        .set    reset_vector,0x0100
        .set    mach_vector,0x0200
        .set    prot_vector,0x0300
        .set    isi_vector,0x0400
        .set    ext_vector,0x0500
        .set    align_vector,0x0600
        .set    prog_vector,0x0700
        .set    float_vector,0x0800
        .set    dec_vector,0x0900
        .set    sys_vector,0x00C00
        .set    trace_vector, 0x0d00
        .set    itm_vector,0x01000
        .set    dltm_vector,0x1100
        .set    dstm_vector,0x1200
        .set    addr_vector,0x1300
        .set    sysmgmt_vector,0x1400
 
/* Go to the right section */
#if PPC_ASM == PPC_ASM_ELF
        .section .vectors,"awx",@progbits
#elif PPC_ASM == PPC_ASM_XCOFF
        .csect  .text[PR]
#endif
 
        PUBLIC_VAR (__vectors)
SYM (__vectors):
 
#if PPCN_60X_USE_DINK
        .org    reset_vector - file_base
        /* This is where the DINK soft reset handler is located */
        ba  0xfff00180
 
        .org    mach_vector - file_base
        ba  0xfff00200
 
        .org    prot_vector - file_base
        ba  0xfff00300
 
        .org    isi_vector - file_base
        ba  0xfff00400
 
        .org    ext_vector - file_base
        rfi
 
        .org    align_vector - file_base
        ba  0xfff00600
 
        .org    prog_vector - file_base
        ba  0xfff00700
 
        .org    float_vector - file_base
        ba  0xfff00800
 
        .org    dec_vector - file_base
        rfi
 
        .org    sys_vector - file_base
        ba  0xfff00C00
 
        .org    trace_vector - file_base
        ba  0xfff00d00
 
        .org    itm_vector - file_base
        ba  0xfff01000
 
        .org    dltm_vector - file_base
        ba  0xfff01100
 
        .org    dstm_vector - file_base
        ba  0xfff01200
 
        .org    addr_vector - file_base
        ba  0xfff01300
 
        .org    sysmgmt_vector - file_base
        ba  0xfff01400
#else
        .org    reset_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,1
display_exc:
        stw             r3,IP_3(r1)
        stw             r5,IP_5(r1)
        /*
         * Enable data and instruction address translation
         */
        li      r3,MSR_IR | MSR_DR
        mtmsr   r3
        lis             r3,0x8000
        stb             r4,0x860(r3)
        addi    r4,r4,0x30
waitfortx:
        lbz             r5,0x3fd(r3)
        andi.   r5,r5,0x20
        beq             waitfortx
        stb             r4,0x3f8(r3)
        li              r5,0
        stw             r4,0x00(r5)
        mfsrr0  r4
        stw             r4,0x04(r5)
        mfsrr1  r4
        stw             r4,0x08(r5)
        lwz             r4,IP_4(r1)
        lwz             r5,IP_5(r1)
        lwz             r3,IP_3(r1)
        addi    r1,r1,IP_END
        rfi
 
        .org    mach_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        stw             r3,IP_3(r1)
        lis             r4,0
        mfspr   r3,srr0
        stw             r3,0x00(r4)
        mfspr   r3,srr1
        stw             r3,0x04(r4)
        stw             r5,0x08(r4)
        stw             r2,0x0c(r4)
        stw             r11,0x10(r4)
        stw             r12,0x14(r4)
        dcbst   0,r4
        li              r4,0x02
        b               display_exc
 
        .org    prot_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x03
        b               display_exc
 
        .org    isi_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x04
        b               display_exc
 
        .org    ext_vector - file_base
        rfi
 
        .org    align_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x06
        b               display_exc
 
        .org    prog_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x07
        b               display_exc
 
        .org    float_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x08
        b               display_exc
 
        .org    dec_vector - file_base
        rfi
 
        .org    sys_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0a
        b               display_exc
 
        .org    trace_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0b
        b               display_exc
 
        .org    itm_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0c
        b               display_exc
 
        .org    dltm_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0d
        b               display_exc
 
        .org    dstm_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0e
        b               display_exc
 
        .org    addr_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x0f
        b               display_exc
 
        .org    sysmgmt_vector - file_base
        stwu    r1, -(IP_END)(r1)
        stw             r4,IP_4(r1)
        li              r4,0x00
        b               display_exc
#endif
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [ppcn_60x/] [vectors/] [vectors.S] - Blame information for rev 607

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* (c) 1998, Radstone Technology plc.`
3			`*`
4			`*`
5			`* This is an unpublished work the copyright in which vests`
6			`* in Radstone Technology plc. All rights reserved.`
7			`*`
8			`* The information contained herein is the property of Radstone`
9			`* Technology plc. and is supplied without liability for`
10			`* errors or omissions and no part may be reproduced, used or`
11			`* disclosed except as authorized by contract or other written`
12			`* permission. The copyright and the foregoing`
13			`* restriction on reproduction, use and disclosure extend to`
14			`* all the media in which this information may be`
15			`* embodied.`
16			`*`
17			`*/`
18			`/* vectors.s 1.1 - 95/12/04`
19			`*`
20			`* This file contains the assembly code for the PowerPC`
21			`* interrupt veneers for RTEMS.`
22			`*`
23			`*/`
24
25			`/*`
26			`* The issue with this file is getting it loaded at the right place.`
27			`* The first vector MUST be at address 0x????0100.`
28			`* How this is achieved is dependant on the tool chain.`
29			`*`
30			`* However the basic mechanism for ELF assemblers is to create a`
31			`* section called ".vectors", which will be loaded to an address`
32			`* between 0x????0000 and 0x????0100 (inclusive) via a link script.`
33			`*`
34			`* The basic mechanism for XCOFF assemblers is to place it in the`
35			`* normal text section, and arrange for this file to be located`
36			`* at an appropriate position on the linker command line.`
37			`*`
38			`* The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the`
39			`* offset from 0x????0000 to the first location in the file. This`
40			`* will usually be 0x0000 or 0x0100.`
41			`*`
42			`* $Id: vectors.S,v 1.2 2001-09-27 12:01:01 chris Exp $`
43			`*/`
44
45			`#include "asm.h"`
46			`#include "bsp.h"`
47
48			`#ifndef PPC_VECTOR_FILE_BASE`
49			`#error "PPC_VECTOR_FILE_BASE is not defined."`
50			`#endif`
51
52			`.set IP_LINK, 0`
53			`#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)`
54			`.set IP_0, (IP_LINK + 56)`
55			`#else`
56			`.set IP_0, (IP_LINK + 8)`
57			`#endif`
58			`.set IP_2, (IP_0 + 4)`
59
60			`.set IP_3, (IP_2 + 4)`
61			`.set IP_4, (IP_3 + 4)`
62			`.set IP_5, (IP_4 + 4)`
63			`.set IP_6, (IP_5 + 4)`
64
65			`.set IP_7, (IP_6 + 4)`
66			`.set IP_8, (IP_7 + 4)`
67			`.set IP_9, (IP_8 + 4)`
68			`.set IP_10, (IP_9 + 4)`
69
70			`.set IP_11, (IP_10 + 4)`
71			`.set IP_12, (IP_11 + 4)`
72			`.set IP_13, (IP_12 + 4)`
73			`.set IP_28, (IP_13 + 4)`
74
75			`.set IP_29, (IP_28 + 4)`
76			`.set IP_30, (IP_29 + 4)`
77			`.set IP_31, (IP_30 + 4)`
78			`.set IP_CR, (IP_31 + 4)`
79
80			`.set IP_CTR, (IP_CR + 4)`
81			`.set IP_XER, (IP_CTR + 4)`
82			`.set IP_LR, (IP_XER + 4)`
83			`.set IP_PC, (IP_LR + 4)`
84
85			`.set IP_MSR, (IP_PC + 4)`
86
87			`.set IP_END, (IP_MSR + 16)`
88
89			`/* Where this file will be loaded */`
90			`.set file_base, PPC_VECTOR_FILE_BASE`
91
92			`/* Vector offsets */`
93			`.set reset_vector,0x0100`
94			`.set mach_vector,0x0200`
95			`.set prot_vector,0x0300`
96			`.set isi_vector,0x0400`
97			`.set ext_vector,0x0500`
98			`.set align_vector,0x0600`
99			`.set prog_vector,0x0700`
100			`.set float_vector,0x0800`
101			`.set dec_vector,0x0900`
102			`.set sys_vector,0x00C00`
103			`.set trace_vector, 0x0d00`
104			`.set itm_vector,0x01000`
105			`.set dltm_vector,0x1100`
106			`.set dstm_vector,0x1200`
107			`.set addr_vector,0x1300`
108			`.set sysmgmt_vector,0x1400`
109
110			`/* Go to the right section */`
111			`#if PPC_ASM == PPC_ASM_ELF`
112			`.section .vectors,"awx",@progbits`
113			`#elif PPC_ASM == PPC_ASM_XCOFF`
114			`.csect .text[PR]`
115			`#endif`
116
117			`PUBLIC_VAR (__vectors)`
118			`SYM (__vectors):`
119
120			`#if PPCN_60X_USE_DINK`
121			`.org reset_vector - file_base`
122			`/* This is where the DINK soft reset handler is located */`
123			`ba 0xfff00180`
124
125			`.org mach_vector - file_base`
126			`ba 0xfff00200`
127
128			`.org prot_vector - file_base`
129			`ba 0xfff00300`
130
131			`.org isi_vector - file_base`
132			`ba 0xfff00400`
133
134			`.org ext_vector - file_base`
135			`rfi`
136
137			`.org align_vector - file_base`
138			`ba 0xfff00600`
139
140			`.org prog_vector - file_base`
141			`ba 0xfff00700`
142
143			`.org float_vector - file_base`
144			`ba 0xfff00800`
145
146			`.org dec_vector - file_base`
147			`rfi`
148
149			`.org sys_vector - file_base`
150			`ba 0xfff00C00`
151
152			`.org trace_vector - file_base`
153			`ba 0xfff00d00`
154
155			`.org itm_vector - file_base`
156			`ba 0xfff01000`
157
158			`.org dltm_vector - file_base`
159			`ba 0xfff01100`
160
161			`.org dstm_vector - file_base`
162			`ba 0xfff01200`
163
164			`.org addr_vector - file_base`
165			`ba 0xfff01300`
166
167			`.org sysmgmt_vector - file_base`
168			`ba 0xfff01400`
169			`#else`
170			`.org reset_vector - file_base`
171			`stwu r1, -(IP_END)(r1)`
172			`stw r4,IP_4(r1)`
173			`li r4,1`
174			`display_exc:`
175			`stw r3,IP_3(r1)`
176			`stw r5,IP_5(r1)`
177			`/*`
178			`* Enable data and instruction address translation`
179			`*/`
180			`li r3,MSR_IR \| MSR_DR`
181			`mtmsr r3`
182			`lis r3,0x8000`
183			`stb r4,0x860(r3)`
184			`addi r4,r4,0x30`
185			`waitfortx:`
186			`lbz r5,0x3fd(r3)`
187			`andi. r5,r5,0x20`
188			`beq waitfortx`
189			`stb r4,0x3f8(r3)`
190			`li r5,0`
191			`stw r4,0x00(r5)`
192			`mfsrr0 r4`
193			`stw r4,0x04(r5)`
194			`mfsrr1 r4`
195			`stw r4,0x08(r5)`
196			`lwz r4,IP_4(r1)`
197			`lwz r5,IP_5(r1)`
198			`lwz r3,IP_3(r1)`
199			`addi r1,r1,IP_END`
200			`rfi`
201
202			`.org mach_vector - file_base`
203			`stwu r1, -(IP_END)(r1)`
204			`stw r4,IP_4(r1)`
205			`stw r3,IP_3(r1)`
206			`lis r4,0`
207			`mfspr r3,srr0`
208			`stw r3,0x00(r4)`
209			`mfspr r3,srr1`
210			`stw r3,0x04(r4)`
211			`stw r5,0x08(r4)`
212			`stw r2,0x0c(r4)`
213			`stw r11,0x10(r4)`
214			`stw r12,0x14(r4)`
215			`dcbst 0,r4`
216			`li r4,0x02`
217			`b display_exc`
218
219			`.org prot_vector - file_base`
220			`stwu r1, -(IP_END)(r1)`
221			`stw r4,IP_4(r1)`
222			`li r4,0x03`
223			`b display_exc`
224
225			`.org isi_vector - file_base`
226			`stwu r1, -(IP_END)(r1)`
227			`stw r4,IP_4(r1)`
228			`li r4,0x04`
229			`b display_exc`
230
231			`.org ext_vector - file_base`
232			`rfi`
233
234			`.org align_vector - file_base`
235			`stwu r1, -(IP_END)(r1)`
236			`stw r4,IP_4(r1)`
237			`li r4,0x06`
238			`b display_exc`
239
240			`.org prog_vector - file_base`
241			`stwu r1, -(IP_END)(r1)`
242			`stw r4,IP_4(r1)`
243			`li r4,0x07`
244			`b display_exc`
245
246			`.org float_vector - file_base`
247			`stwu r1, -(IP_END)(r1)`
248			`stw r4,IP_4(r1)`
249			`li r4,0x08`
250			`b display_exc`
251
252			`.org dec_vector - file_base`
253			`rfi`
254
255			`.org sys_vector - file_base`
256			`stwu r1, -(IP_END)(r1)`
257			`stw r4,IP_4(r1)`
258			`li r4,0x0a`
259			`b display_exc`
260
261			`.org trace_vector - file_base`
262			`stwu r1, -(IP_END)(r1)`
263			`stw r4,IP_4(r1)`
264			`li r4,0x0b`
265			`b display_exc`
266
267			`.org itm_vector - file_base`
268			`stwu r1, -(IP_END)(r1)`
269			`stw r4,IP_4(r1)`
270			`li r4,0x0c`
271			`b display_exc`
272
273			`.org dltm_vector - file_base`
274			`stwu r1, -(IP_END)(r1)`
275			`stw r4,IP_4(r1)`
276			`li r4,0x0d`
277			`b display_exc`
278
279			`.org dstm_vector - file_base`
280			`stwu r1, -(IP_END)(r1)`
281			`stw r4,IP_4(r1)`
282			`li r4,0x0e`
283			`b display_exc`
284
285			`.org addr_vector - file_base`
286			`stwu r1, -(IP_END)(r1)`
287			`stw r4,IP_4(r1)`
288			`li r4,0x0f`
289			`b display_exc`
290
291			`.org sysmgmt_vector - file_base`
292			`stwu r1, -(IP_END)(r1)`
293			`stw r4,IP_4(r1)`
294			`li r4,0x00`
295			`b display_exc`
296			`#endif`
297