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unneback |
/* align_h.s 1.1 - 95/12/04
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*
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* This file contains the assembly code for the PowerPC 403
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* alignment exception handler for RTEMS.
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*
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* Based upon IBM provided code with the following release:
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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* Modifications:
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*
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* Author: Andrew Bray
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*
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of i-cubed limited not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* i-cubed limited makes no representations about the suitability
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* of this software for any purpose.
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*
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* $Id: align_h.S,v 1.2 2001-09-27 12:01:03 chris Exp $
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*/
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#include "asm.h"
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#include "bsp.h"
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.set CACHE_SIZE,16 # cache line size of 32 bytes
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.set CACHE_SIZE_L2,4 # cache line size, log 2
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.set Open_gpr0,0
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.set Open_gpr1,4
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.set Open_gpr2,8
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.set Open_gpr3,12
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.set Open_gpr4,16
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.set Open_gpr5,20
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.set Open_gpr6,24
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.set Open_gpr7,28
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.set Open_gpr8,32
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.set Open_gpr9,36
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.set Open_gpr10,40
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.set Open_gpr11,44
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.set Open_gpr12,48
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.set Open_gpr13,52
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.set Open_gpr14,56
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.set Open_gpr15,60
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.set Open_gpr16,64
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.set Open_gpr17,68
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.set Open_gpr18,72
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.set Open_gpr19,76
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.set Open_gpr20,80
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.set Open_gpr21,84
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.set Open_gpr22,88
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.set Open_gpr23,92
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.set Open_gpr24,96
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.set Open_gpr25,100
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.set Open_gpr26,104
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.set Open_gpr27,108
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.set Open_gpr28,112
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.set Open_gpr29,116
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.set Open_gpr30,120
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.set Open_gpr31,124
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.set Open_xer,128
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.set Open_lr,132
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.set Open_ctr,136
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.set Open_cr,140
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.set Open_srr2,144
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.set Open_srr3,148
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.set Open_srr0,152
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.set Open_srr1,156
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/*
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* This code makes several assumptions for processing efficiency
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* * General purpose registers are continuous in the image, beginning with
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* Open_gpr0
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* * Hash table is highly dependent on opcodes - opcode changes *will*
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* require rework of the instruction decode mechanism.
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*/
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.text
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.globl align_h
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.align CACHE_SIZE_L2
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align_h:
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/*-----------------------------------------------------------------------
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* Store GPRs in Open Reg save area
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* Set up r2 as base reg, r1 pointing to Open Reg save area
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*----------------------------------------------------------------------*/
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stmw r0,ALIGN_REGS(r0)
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li r1,ALIGN_REGS
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/*-----------------------------------------------------------------------
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* Store special purpose registers in reg save area
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*----------------------------------------------------------------------*/
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mfxer r7
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mflr r8
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mfcr r9
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mfctr r10
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stw r7,Open_xer(r1)
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stw r8,Open_lr(r1)
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stw r9,Open_cr(r1)
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stw r10,Open_ctr(r1)
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mfspr r7, srr2 /* SRR 2 */
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mfspr r8, srr3 /* SRR 3 */
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mfspr r9, srr0 /* SRR 0 */
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mfspr r10, srr1 /* SRR 1 */
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stw r7,Open_srr2(r1)
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stw r8,Open_srr3(r1)
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stw r9,Open_srr0(r1)
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stw r10,Open_srr1(r1)
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/* Set up common registers */
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mfspr r5, dear /* DEAR: R5 is data exception address */
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lwz r9,Open_srr0(r1) /* get faulting instruction */
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addi r7,r9,4 /* bump instruction */
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stw r7,Open_srr0(r1) /* restore to image */
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lwz r9, 0(r9) /* retrieve actual instruction */
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rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
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rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
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bl ref_point /* establish addressibility */
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ref_point:
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mflr r11 /* r11 is the anchor point for ref_point */
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addi r10, r7, -31 /* r10 = r7 - 31 */
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rlwinm r10,r10,2,2,31 /* r10 *= 4 */
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add r10, r10, r11 /* r10 += anchor point */
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lwz r10, primary_jt-ref_point(r10)
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mtlr r10
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rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
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la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
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blr
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primary_jt:
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.long xform
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.long lwz
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.long lwzu
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.long 0
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.long 0
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.long stw
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.long stwu
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.long 0
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.long 0
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.long lhz
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.long lhzu
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.long lha
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.long lhau
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.long sth
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.long sthu
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.long lmw
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.long stmw
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/*
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* handlers
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*/
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/*
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* xform instructions require an additional decode. Fortunately, a relatively
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* simple hash step breaks the instructions out with no collisions
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*/
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xform:
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rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
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rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
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add r10,r7,r10 /* r10 = r7 + r10 */
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rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
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add r10,r10,r11 /* r10 += anchor point */
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lwz r10, secondary_ht-ref_point(r10)
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mtlr r10
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la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
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rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
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blrl
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secondary_ht:
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.long lhzux /* b 0 0x137 */
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.long lhax /* b 1 0x157 */
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.long lhaux /* b 2 0x177 */
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.long sthx /* b 3 0x197 */
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.long sthux /* b 4 0x1b7 */
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.long 0 /* b 5 */
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.long lwbrx /* b 6 0x216 */
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.long 0 /* b 7 */
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.long 0 /* b 8 */
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.long 0 /* b 9 */
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.long stwbrx /* b A 0x296 */
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.long 0 /* b B */
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.long 0 /* b C */
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.long 0 /* b D */
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.long lhbrx /* b E 0x316 */
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.long 0 /* b F */
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.long 0 /* b 10 */
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.long 0 /* b 11 */
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.long sthbrx /* b 12 0x396 */
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.long 0 /* b 13 */
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.long lwarx /* b 14 0x014 */
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.long dcbz /* b 15 0x3f6 */
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.long 0 /* b 16 */
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.long lwzx /* b 17 0x017 */
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.long lwzux /* b 18 0x037 */
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.long 0 /* b 19 */
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.long stwcx /* b 1A 0x096 */
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.long stwx /* b 1B 0x097 */
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.long stwux /* b 1C 0x0B7 */
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.long 0 /* b 1D */
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.long 0 /* b 1E */
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.long lhzx /* b 1F 0x117 */
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/*
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* for all handlers
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* r4 - Addressability to interrupt context
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* r5 - DEAR address (faulting data address)
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* r6 - RA field * 4
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| 228 |
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* r7 - Address of GPR 0 in image
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| 229 |
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* r8 - RD field * 4
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| 230 |
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* r9 - Failing instruction
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*/
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| 233 |
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/* Load halfword algebraic with update */
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| 234 |
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lhau:
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| 235 |
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/* Load halfword algebraic with update indexed */
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lhaux:
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| 237 |
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stwx r5,r7,r6 /* update RA with effective addr */
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| 238 |
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| 239 |
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/* Load halfword algebraic */
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| 240 |
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lha:
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| 241 |
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/* Load halfword algebraic indexed */
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| 242 |
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lhax:
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| 243 |
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lswi r10,r5,2 /* load two bytes into r10 */
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srawi r10,r10,16 /* shift right 2 bytes, extending sign */
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| 245 |
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stwx r10,r7,r8 /* update reg image */
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| 246 |
|
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b align_complete /* return */
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| 247 |
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| 248 |
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/* Load Half Word Byte-Reversed Indexed */
|
| 249 |
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lhbrx:
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| 250 |
|
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lswi r10,r5,2 /* load two bytes from DEAR into r10 */
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| 251 |
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rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
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| 252 |
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stwbrx r10,r7,r8 /* store reversed in reg image */
|
| 253 |
|
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b align_complete /* return */
|
| 254 |
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| 255 |
|
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/* Load Half Word and Zero with Update */
|
| 256 |
|
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lhzu:
|
| 257 |
|
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/* Load Half Word and Zero with Update Indexed */
|
| 258 |
|
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lhzux:
|
| 259 |
|
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stwx r5,r7,r6 /* update RA with effective addr */
|
| 260 |
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|
| 261 |
|
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/* Load Half Word and Zero */
|
| 262 |
|
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lhz:
|
| 263 |
|
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/* Load Half Word and Zero Indexed */
|
| 264 |
|
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lhzx:
|
| 265 |
|
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lswi r10,r5,2 /* load two bytes from DEAR into r10 */
|
| 266 |
|
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rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
|
| 267 |
|
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stwx r10,r7,r8 /* update reg image */
|
| 268 |
|
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b align_complete /* return */
|
| 269 |
|
|
|
| 270 |
|
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/*
|
| 271 |
|
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* Load Multiple Word
|
| 272 |
|
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*/
|
| 273 |
|
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lmw:
|
| 274 |
|
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lwzx r9,r6,r7 /* R9 contains saved value of RA */
|
| 275 |
|
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addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
| 276 |
|
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rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
| 277 |
|
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subfic r8,r8,32 /* r8 is reg count to load */
|
| 278 |
|
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mtctr r8 /* load counter */
|
| 279 |
|
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addi r8,r8,-1 /* r8-- */
|
| 280 |
|
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rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
| 281 |
|
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add r5,r5,r8 /* update DEAR to point to last reg */
|
| 282 |
|
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lwmloop:
|
| 283 |
|
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lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
|
| 284 |
|
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stwu r11,-4(r10) /* load image and decrement pointer */
|
| 285 |
|
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addi r5,r5,-4 /* decrement effective address */
|
| 286 |
|
|
bdnz lwmloop
|
| 287 |
|
|
stwx r9,r6,r7 /* restore RA (in case it was trashed) */
|
| 288 |
|
|
b align_complete /* return */
|
| 289 |
|
|
|
| 290 |
|
|
/*
|
| 291 |
|
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* Load Word and Reserve Indexed
|
| 292 |
|
|
*/
|
| 293 |
|
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lwarx:
|
| 294 |
|
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lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
| 295 |
|
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stwx r10,r7,r8 /* update reg image */
|
| 296 |
|
|
rlwinm r5,r5,0,0,29 /* Word align address */
|
| 297 |
|
|
lwarx r10,0,r5 /* Set reservation */
|
| 298 |
|
|
b align_complete /* return */
|
| 299 |
|
|
|
| 300 |
|
|
/*
|
| 301 |
|
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* Load Word Byte-Reversed Indexed
|
| 302 |
|
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*/
|
| 303 |
|
|
lwbrx:
|
| 304 |
|
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lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
| 305 |
|
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stwbrx r10,r7,r8 /* store reversed in reg image */
|
| 306 |
|
|
b align_complete /* return */
|
| 307 |
|
|
|
| 308 |
|
|
/* Load Word and Zero with Update */
|
| 309 |
|
|
lwzu:
|
| 310 |
|
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/* Load Word and Zero with Update Indexed */
|
| 311 |
|
|
lwzux:
|
| 312 |
|
|
stwx r5,r7,r6 /* update RA with effective addr */
|
| 313 |
|
|
|
| 314 |
|
|
/* Load Word and Zero */
|
| 315 |
|
|
lwz:
|
| 316 |
|
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/* Load Word and Zero Indexed */
|
| 317 |
|
|
lwzx:
|
| 318 |
|
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
| 319 |
|
|
stwx r10,r7,r8 /* update reg image */
|
| 320 |
|
|
b align_complete /* return */
|
| 321 |
|
|
|
| 322 |
|
|
/* Store instructions */
|
| 323 |
|
|
|
| 324 |
|
|
/* */
|
| 325 |
|
|
/* Store Half Word and Update */
|
| 326 |
|
|
sthu:
|
| 327 |
|
|
/* Store Half Word and Update Indexed */
|
| 328 |
|
|
sthux:
|
| 329 |
|
|
stwx r5,r7,r6 /* Update RA with effective address */
|
| 330 |
|
|
|
| 331 |
|
|
/* Store Half Word */
|
| 332 |
|
|
sth:
|
| 333 |
|
|
/* Store Half Word Indexed */
|
| 334 |
|
|
sthx:
|
| 335 |
|
|
lwzx r10,r8,r7 /* retrieve source register value */
|
| 336 |
|
|
rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
|
| 337 |
|
|
stswi r10,r5,2 /* store bytes to DEAR address */
|
| 338 |
|
|
b align_complete /* return */
|
| 339 |
|
|
|
| 340 |
|
|
/* */
|
| 341 |
|
|
/* Store Half Word Byte-Reversed Indexed */
|
| 342 |
|
|
sthbrx:
|
| 343 |
|
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
| 344 |
|
|
stswi r10,r5,2 /* move two bytes to DEAR address */
|
| 345 |
|
|
b align_complete /* return */
|
| 346 |
|
|
|
| 347 |
|
|
/* */
|
| 348 |
|
|
/* Store Multiple Word */
|
| 349 |
|
|
stmw:
|
| 350 |
|
|
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
| 351 |
|
|
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
| 352 |
|
|
subfic r8,r8,32 /* r8 is reg count to load */
|
| 353 |
|
|
mtctr r8 /* load counter */
|
| 354 |
|
|
addi r8,r8,-1 /* r8-- */
|
| 355 |
|
|
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
| 356 |
|
|
add r5,r5,r8 /* update DEAR to point to last reg */
|
| 357 |
|
|
stmloop:
|
| 358 |
|
|
lwzu r11,-4(r10) /* get register value */
|
| 359 |
|
|
stswi r11,r5,4 /* output to DEAR address */
|
| 360 |
|
|
addi r5,r5,-4 /* decrement effective address */
|
| 361 |
|
|
bdnz stmloop
|
| 362 |
|
|
b align_complete /* return */
|
| 363 |
|
|
|
| 364 |
|
|
/* */
|
| 365 |
|
|
/* Store Word and Update */
|
| 366 |
|
|
stwu:
|
| 367 |
|
|
/* Store Word and Update Indexed */
|
| 368 |
|
|
stwux:
|
| 369 |
|
|
stwx r5,r7,r6 /* Update RA with effective address */
|
| 370 |
|
|
|
| 371 |
|
|
/* Store Word */
|
| 372 |
|
|
stw:
|
| 373 |
|
|
/* Store Word Indexed */
|
| 374 |
|
|
stwx:
|
| 375 |
|
|
lwzx r10,r8,r7 /* retrieve source register value */
|
| 376 |
|
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
| 377 |
|
|
b align_complete /* return */
|
| 378 |
|
|
|
| 379 |
|
|
/* */
|
| 380 |
|
|
/* Store Word Byte-Reversed Indexed */
|
| 381 |
|
|
stwbrx:
|
| 382 |
|
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
| 383 |
|
|
stswi r10,r5,4 /* move two bytes to DEAR address */
|
| 384 |
|
|
b align_complete /* return */
|
| 385 |
|
|
|
| 386 |
|
|
/* */
|
| 387 |
|
|
/* Store Word Conditional Indexed */
|
| 388 |
|
|
stwcx:
|
| 389 |
|
|
rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
|
| 390 |
|
|
lwz r11,0(r10) /* save original value of store */
|
| 391 |
|
|
stwcx. r11,r0,r10 /* attempt store to address */
|
| 392 |
|
|
bne stwcx_moveon /* store failed, move on */
|
| 393 |
|
|
stw r11,0(r10) /* repair damage */
|
| 394 |
|
|
lwzx r9,r7,r8 /* get register value */
|
| 395 |
|
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
| 396 |
|
|
stwcx_moveon:
|
| 397 |
|
|
mfcr r11 /* get condition reg */
|
| 398 |
|
|
lwz r9,Open_cr(r1) /* get condition reg image */
|
| 399 |
|
|
rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
|
| 400 |
|
|
lwz r11,Open_xer(r1) /* get XER reg */
|
| 401 |
|
|
rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
|
| 402 |
|
|
stw r9,Open_cr(r1) /* store cr image */
|
| 403 |
|
|
b align_complete /* return */
|
| 404 |
|
|
|
| 405 |
|
|
/* */
|
| 406 |
|
|
/* Data Cache Block Zero */
|
| 407 |
|
|
dcbz:
|
| 408 |
|
|
rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
|
| 409 |
|
|
/* get address to nearest Cache line */
|
| 410 |
|
|
addi r5,r5,-4 /* adjust by a word */
|
| 411 |
|
|
addi r10,r0,CACHE_SIZE/4 /* set counter value */
|
| 412 |
|
|
mtctr r10
|
| 413 |
|
|
addi r11,r0,0 /* r11 = 0 */
|
| 414 |
|
|
dcbz_loop:
|
| 415 |
|
|
stwu r11,4(r5) /* store a word and update EA */
|
| 416 |
|
|
bdnz dcbz_loop
|
| 417 |
|
|
b align_complete /* return */
|
| 418 |
|
|
|
| 419 |
|
|
align_complete:
|
| 420 |
|
|
/*-----------------------------------------------------------------------
|
| 421 |
|
|
* Restore regs and return from the interrupt
|
| 422 |
|
|
*----------------------------------------------------------------------*/
|
| 423 |
|
|
lmw r24,Open_xer+ALIGN_REGS(r0)
|
| 424 |
|
|
mtxer r24
|
| 425 |
|
|
mtlr r25
|
| 426 |
|
|
mtctr r26
|
| 427 |
|
|
mtcrf 0xFF, r27
|
| 428 |
|
|
mtspr srr2, r28 /* SRR 2 */
|
| 429 |
|
|
mtspr srr3, r29 /* SRR 3 */
|
| 430 |
|
|
mtspr srr0, r30 /* SRR 0 */
|
| 431 |
|
|
mtspr srr1, r31 /* SRR 1 */
|
| 432 |
|
|
lmw r1,Open_gpr1+ALIGN_REGS(r0)
|
| 433 |
|
|
lwz r0,Open_gpr0+ALIGN_REGS(r0)
|
| 434 |
|
|
rfi
|
