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/*  align_h.s   1.1 - 95/12/04
2
 *
3
 *  This file contains the assembly code for the PowerPC 403
4
 *  alignment exception handler for RTEMS.
5
 *
6
 *  Based upon IBM provided code with the following release:
7
 *
8
 *  This source code has been made available to you by IBM on an AS-IS
9
 *  basis.  Anyone receiving this source is licensed under IBM
10
 *  copyrights to use it in any way he or she deems fit, including
11
 *  copying it, modifying it, compiling it, and redistributing it either
12
 *  with or without modifications.  No license under IBM patents or
13
 *  patent applications is to be implied by the copyright license.
14
 *
15
 *  Any user of this software should understand that IBM cannot provide
16
 *  technical support for this software and will not be responsible for
17
 *  any consequences resulting from the use of this software.
18
 *
19
 *  Any person who transfers this source code or any derivative work
20
 *  must include the IBM copyright notice, this paragraph, and the
21
 *  preceding two paragraphs in the transferred software.
22
 *
23
 *      COPYRIGHT   I B M   CORPORATION 1995
24
 *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
25
 *
26
 * Modifications:
27
 *
28
 *  Author:     Andrew Bray 
29
 *
30
 *  COPYRIGHT (c) 1995 by i-cubed ltd.
31
 *
32
 *  To anyone who acknowledges that this file is provided "AS IS"
33
 *  without any express or implied warranty:
34
 *      permission to use, copy, modify, and distribute this file
35
 *      for any purpose is hereby granted without fee, provided that
36
 *      the above copyright notice and this notice appears in all
37
 *      copies, and that the name of i-cubed limited not be used in
38
 *      advertising or publicity pertaining to distribution of the
39
 *      software without specific, written prior permission.
40
 *      i-cubed limited makes no representations about the suitability
41
 *      of this software for any purpose.
42
 *
43
 *  $Id: align_h.S,v 1.2 2001-09-27 12:01:03 chris Exp $
44
 */
45
 
46
#include "asm.h"
47
#include "bsp.h"
48
 
49
.set    CACHE_SIZE,16           # cache line size of 32 bytes
50
.set    CACHE_SIZE_L2,4         # cache line size, log 2
51
 
52
.set    Open_gpr0,0
53
.set    Open_gpr1,4
54
.set    Open_gpr2,8
55
.set    Open_gpr3,12
56
.set    Open_gpr4,16
57
.set    Open_gpr5,20
58
.set    Open_gpr6,24
59
.set    Open_gpr7,28
60
.set    Open_gpr8,32
61
.set    Open_gpr9,36
62
.set    Open_gpr10,40
63
.set    Open_gpr11,44
64
.set    Open_gpr12,48
65
.set    Open_gpr13,52
66
.set    Open_gpr14,56
67
.set    Open_gpr15,60
68
.set    Open_gpr16,64
69
.set    Open_gpr17,68
70
.set    Open_gpr18,72
71
.set    Open_gpr19,76
72
.set    Open_gpr20,80
73
.set    Open_gpr21,84
74
.set    Open_gpr22,88
75
.set    Open_gpr23,92
76
.set    Open_gpr24,96
77
.set    Open_gpr25,100
78
.set    Open_gpr26,104
79
.set    Open_gpr27,108
80
.set    Open_gpr28,112
81
.set    Open_gpr29,116
82
.set    Open_gpr30,120
83
.set    Open_gpr31,124
84
.set    Open_xer,128
85
.set    Open_lr,132
86
.set    Open_ctr,136
87
.set    Open_cr,140
88
.set    Open_srr2,144
89
.set    Open_srr3,148
90
.set    Open_srr0,152
91
.set    Open_srr1,156
92
 
93
 
94
/*
95
 *  This code makes several assumptions for processing efficiency
96
 *  *  General purpose registers are continuous in the image, beginning with
97
 *     Open_gpr0
98
 *  *  Hash table is highly dependent on opcodes - opcode changes *will*
99
 *     require rework of the instruction decode mechanism.
100
 */
101
 
102
        .text
103
        .globl  align_h
104
 
105
        .align  CACHE_SIZE_L2
106
align_h:
107
        /*-----------------------------------------------------------------------
108
         * Store GPRs in Open Reg save area
109
         * Set up r2 as base reg, r1 pointing to Open Reg save area
110
         *----------------------------------------------------------------------*/
111
        stmw    r0,ALIGN_REGS(r0)
112
        li      r1,ALIGN_REGS
113
        /*-----------------------------------------------------------------------
114
         * Store special purpose registers in reg save area
115
         *----------------------------------------------------------------------*/
116
        mfxer   r7
117
        mflr    r8
118
        mfcr    r9
119
        mfctr   r10
120
        stw     r7,Open_xer(r1)
121
        stw     r8,Open_lr(r1)
122
        stw     r9,Open_cr(r1)
123
        stw     r10,Open_ctr(r1)
124
        mfspr   r7, srr2                /* SRR 2 */
125
        mfspr   r8, srr3                /* SRR 3 */
126
        mfspr   r9, srr0                /* SRR 0 */
127
        mfspr   r10, srr1               /* SRR 1 */
128
        stw     r7,Open_srr2(r1)
129
        stw     r8,Open_srr3(r1)
130
        stw     r9,Open_srr0(r1)
131
        stw     r10,Open_srr1(r1)
132
 
133
/*      Set up common registers */
134
        mfspr   r5, dear                /* DEAR: R5 is data exception address */
135
        lwz     r9,Open_srr0(r1)        /* get faulting instruction */
136
        addi    r7,r9,4                 /* bump instruction */
137
        stw     r7,Open_srr0(r1)        /* restore to image */
138
        lwz     r9, 0(r9)               /* retrieve actual instruction */
139
        rlwinm  r6,r9,18,25,29          /* r6 is RA * 4 field from instruction */
140
        rlwinm  r7,r9,6,26,31           /* r7 is primary opcode */
141
        bl      ref_point               /* establish addressibility */
142
ref_point:
143
        mflr    r11                     /* r11 is the anchor point for ref_point */
144
        addi    r10, r7, -31            /* r10 = r7 - 31 */
145
        rlwinm  r10,r10,2,2,31          /* r10 *= 4 */
146
        add     r10, r10, r11           /* r10 += anchor point */
147
        lwz     r10, primary_jt-ref_point(r10)
148
        mtlr    r10
149
        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
150
        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
151
        blr
152
primary_jt:
153
        .long   xform
154
        .long   lwz
155
        .long   lwzu
156
        .long   0
157
        .long   0
158
        .long   stw
159
        .long   stwu
160
        .long   0
161
        .long   0
162
        .long   lhz
163
        .long   lhzu
164
        .long   lha
165
        .long   lhau
166
        .long   sth
167
        .long   sthu
168
        .long   lmw
169
        .long   stmw
170
/*
171
 *   handlers
172
 */
173
/*
174
 * xform instructions require an additional decode.  Fortunately, a relatively
175
 * simple hash step breaks the instructions out with no collisions
176
 */
177
xform:
178
        rlwinm  r7,r9,31,22,31          /* r7 is secondary opcode */
179
        rlwinm  r10,r7,27,5,31          /* r10 = r7 >> 5 */
180
        add     r10,r7,r10              /* r10 = r7 + r10 */
181
        rlwinm  r10,r10,2,25,29         /* r10 = (r10 & 0x1F) * 4 */
182
        add     r10,r10,r11             /* r10 += anchor point */
183
        lwz     r10, secondary_ht-ref_point(r10)
184
        mtlr    r10
185
        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
186
        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
187
        blrl
188
 
189
secondary_ht:
190
        .long   lhzux                   /* b 0  0x137 */
191
        .long   lhax                    /* b 1  0x157 */
192
        .long   lhaux                   /* b 2  0x177 */
193
        .long   sthx                    /* b 3  0x197 */
194
        .long   sthux                   /* b 4  0x1b7 */
195
        .long   0                       /* b 5 */
196
        .long   lwbrx                   /* b 6  0x216 */
197
        .long   0                       /* b 7 */
198
        .long   0                       /* b 8 */
199
        .long   0                       /* b 9 */
200
        .long   stwbrx                  /* b A  0x296 */
201
        .long   0                       /* b B */
202
        .long   0                       /* b C */
203
        .long   0                       /* b D */
204
        .long   lhbrx                   /* b E   0x316 */
205
        .long   0                       /* b F */
206
        .long   0                       /* b 10 */
207
        .long   0                       /* b 11 */
208
        .long   sthbrx                  /* b 12  0x396 */
209
        .long   0                       /* b 13 */
210
        .long   lwarx                   /* b 14  0x014 */
211
        .long   dcbz                    /* b 15  0x3f6 */
212
        .long   0                       /* b 16 */
213
        .long   lwzx                    /* b 17  0x017 */
214
        .long   lwzux                   /* b 18  0x037 */
215
        .long   0                       /* b 19 */
216
        .long   stwcx                   /* b 1A  0x096 */
217
        .long   stwx                    /* b 1B  0x097 */
218
        .long   stwux                   /* b 1C  0x0B7 */
219
        .long   0                       /* b 1D */
220
        .long   0                       /* b 1E */
221
        .long   lhzx                    /* b 1F 0x117 */
222
 
223
/*
224
 * for all handlers
225
 *       r4 - Addressability to interrupt context
226
 *       r5 - DEAR address (faulting data address)
227
 *       r6 - RA field * 4
228
 *       r7 - Address of GPR 0 in image
229
 *       r8 - RD field * 4
230
 *       r9 - Failing instruction
231
 */
232
 
233
/*       Load halfword algebraic with update */
234
lhau:
235
/*       Load halfword algebraic with update indexed */
236
lhaux:
237
        stwx    r5,r7,r6                /* update RA with effective addr */
238
 
239
/*       Load halfword algebraic */
240
lha:
241
/*       Load halfword algebraic indexed */
242
lhax:
243
        lswi    r10,r5,2                /* load two bytes into r10 */
244
        srawi   r10,r10,16              /* shift right 2 bytes, extending sign */
245
        stwx    r10,r7,r8               /* update reg image */
246
        b       align_complete          /* return */
247
 
248
/*       Load Half Word Byte-Reversed Indexed */
249
lhbrx:
250
        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
251
        rlwinm  r10,r10,0,0,15          /* mask off lower 2 bytes */
252
        stwbrx  r10,r7,r8               /* store reversed in reg image */
253
        b       align_complete          /* return */
254
 
255
/*       Load Half Word and Zero with Update */
256
lhzu:
257
/*       Load Half Word and Zero with Update Indexed */
258
lhzux:
259
        stwx    r5,r7,r6                /* update RA with effective addr */
260
 
261
/*       Load Half Word and Zero */
262
lhz:
263
/*       Load Half Word and Zero Indexed */
264
lhzx:
265
        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
266
        rlwinm  r10,r10,16,16,31        /* shift right 2 bytes, with zero fill */
267
        stwx    r10,r7,r8               /* update reg image */
268
        b       align_complete          /* return */
269
 
270
/*
271
 *       Load Multiple Word
272
 */
273
lmw:
274
        lwzx    r9,r6,r7                /* R9 contains saved value of RA */
275
        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
276
        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
277
        subfic  r8,r8,32                /* r8 is reg count to load */
278
        mtctr   r8                      /* load counter */
279
        addi    r8,r8,-1                /* r8-- */
280
        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
281
        add     r5,r5,r8                /* update DEAR to point to last reg */
282
lwmloop:
283
        lswi    r11,r5,4                /* load r11 with 4 bytes from DEAR */
284
        stwu    r11,-4(r10)             /* load image and decrement pointer */
285
        addi    r5,r5,-4                /* decrement effective address */
286
        bdnz    lwmloop
287
        stwx    r9,r6,r7                /* restore RA (in case it was trashed) */
288
        b       align_complete          /* return */
289
 
290
/*
291
 *       Load Word and Reserve Indexed
292
 */
293
lwarx:
294
        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
295
        stwx    r10,r7,r8               /* update reg image */
296
        rlwinm  r5,r5,0,0,29            /* Word align address */
297
        lwarx   r10,0,r5                /* Set reservation */
298
        b       align_complete          /* return */
299
 
300
/*
301
 *       Load Word Byte-Reversed Indexed
302
 */
303
lwbrx:
304
        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
305
        stwbrx  r10,r7,r8               /* store reversed in reg image */
306
        b       align_complete          /* return */
307
 
308
/*       Load Word and Zero with Update */
309
lwzu:
310
/*       Load Word and Zero with Update Indexed */
311
lwzux:
312
        stwx    r5,r7,r6                /* update RA with effective addr */
313
 
314
/*       Load Word and Zero */
315
lwz:
316
/*       Load Word and Zero Indexed */
317
lwzx:
318
        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
319
        stwx    r10,r7,r8               /* update reg image */
320
        b       align_complete          /* return */
321
 
322
/*    Store instructions */
323
 
324
/* */
325
/*       Store Half Word and Update */
326
sthu:
327
/*       Store Half Word and Update Indexed */
328
sthux:
329
        stwx    r5,r7,r6                /* Update RA with effective address */
330
 
331
/*       Store Half Word */
332
sth:
333
/*       Store Half Word Indexed */
334
sthx:
335
        lwzx    r10,r8,r7               /* retrieve source register value */
336
        rlwinm  r10,r10,16,0,15         /* move two bytes to high end of reg */
337
        stswi   r10,r5,2                /* store bytes to DEAR address */
338
        b       align_complete          /* return */
339
 
340
/* */
341
/*       Store Half Word Byte-Reversed Indexed */
342
sthbrx:
343
        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
344
        stswi   r10,r5,2                /* move two bytes to DEAR address */
345
        b       align_complete          /* return */
346
 
347
/* */
348
/*       Store Multiple Word */
349
stmw:
350
        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
351
        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
352
        subfic  r8,r8,32                /* r8 is reg count to load */
353
        mtctr   r8                      /* load counter */
354
        addi    r8,r8,-1                /* r8-- */
355
        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
356
        add     r5,r5,r8                /* update DEAR to point to last reg */
357
stmloop:
358
        lwzu    r11,-4(r10)             /* get register value */
359
        stswi   r11,r5,4                /* output to DEAR address */
360
        addi    r5,r5,-4                /* decrement effective address */
361
        bdnz    stmloop
362
        b       align_complete          /* return */
363
 
364
/* */
365
/*       Store Word and Update */
366
stwu:
367
/*       Store Word and Update Indexed */
368
stwux:
369
        stwx    r5,r7,r6                /* Update RA with effective address */
370
 
371
/*       Store Word */
372
stw:
373
/*       Store Word Indexed */
374
stwx:
375
        lwzx    r10,r8,r7               /* retrieve source register value */
376
        stswi   r10,r5,4                /* store bytes to DEAR address */
377
        b       align_complete          /* return */
378
 
379
/* */
380
/*       Store Word Byte-Reversed Indexed */
381
stwbrx:
382
        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
383
        stswi   r10,r5,4                /* move two bytes to DEAR address */
384
        b       align_complete          /* return */
385
 
386
/* */
387
/*       Store Word Conditional Indexed */
388
stwcx:
389
        rlwinm  r10,r5,0,0,29           /* r10 = word aligned DEAR */
390
        lwz     r11,0(r10)              /* save original value of store */
391
        stwcx.  r11,r0,r10              /* attempt store to address */
392
        bne     stwcx_moveon            /* store failed, move on */
393
        stw     r11,0(r10)              /* repair damage */
394
        lwzx    r9,r7,r8                /* get register value */
395
        stswi   r10,r5,4                /* store bytes to DEAR address */
396
stwcx_moveon:
397
        mfcr    r11                     /* get condition reg */
398
        lwz     r9,Open_cr(r1)          /* get condition reg image */
399
        rlwimi  r9,r11,0,0,2            /* insert 3 CR bits into cr image */
400
        lwz     r11,Open_xer(r1)        /* get XER reg */
401
        rlwimi  r9,r11,29,2,2           /* insert XER SO bit into cr image */
402
        stw     r9,Open_cr(r1)          /* store cr image */
403
        b       align_complete          /* return */
404
 
405
/* */
406
/*       Data Cache Block Zero */
407
dcbz:
408
        rlwinm  r5,r5,0,0,31-CACHE_SIZE_L2
409
                                        /* get address to nearest Cache line */
410
        addi    r5,r5,-4                /* adjust by a word */
411
        addi    r10,r0,CACHE_SIZE/4     /* set counter value */
412
        mtctr   r10
413
        addi    r11,r0,0                /* r11 = 0 */
414
dcbz_loop:
415
        stwu    r11,4(r5)               /* store a word and update EA */
416
        bdnz    dcbz_loop
417
        b       align_complete          /* return */
418
 
419
align_complete:
420
        /*-----------------------------------------------------------------------
421
         * Restore regs and return from the interrupt
422
         *----------------------------------------------------------------------*/
423
        lmw     r24,Open_xer+ALIGN_REGS(r0)
424
        mtxer   r24
425
        mtlr    r25
426
        mtctr   r26
427
        mtcrf   0xFF, r27
428
        mtspr   srr2, r28               /* SRR 2 */
429
        mtspr   srr3, r29               /* SRR 3 */
430
        mtspr   srr0, r30               /* SRR 0 */
431
        mtspr   srr1, r31               /* SRR 1 */
432
        lmw     r1,Open_gpr1+ALIGN_REGS(r0)
433
        lwz     r0,Open_gpr0+ALIGN_REGS(r0)
434
        rfi

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