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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [score603e/] [PCI_bus/] [universe.c] - Blame information for rev 173

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1 30 unneback
/*
2
 *
3
 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
4
 *  On-Line Applications Research Corporation (OAR).
5
 *  All rights assigned to U.S. Government, 1994.
6
 *
7
 *  This material may be reproduced by or for the U.S. Government pursuant
8
 *  to the copyright license under the clause at DFARS 252.227-7013.  This
9
 *  notice must appear in all copies of this file and its derivatives.
10
 *
11
 * $ld:
12
 */
13
 
14
#include <rtems.h>
15
#include <assert.h>
16
#include <stdio.h>
17
 
18
#include <bsp.h>
19
#include "PCI.h"
20
 
21
/********************************************************************
22
 ********************************************************************
23
 *********                                                  *********
24
 *********                  Prototypes                      *********
25
 *********                                                  *********
26
 ********************************************************************
27
 ********************************************************************/
28
 
29
 
30
/********************************************************************
31
 ********************************************************************
32
 *********                                                  *********
33
 *********                                                  *********
34
 *********                                                  *********
35
 ********************************************************************
36
 ********************************************************************/
37
 
38
typedef struct {
39
  rtems_unsigned32 PCI_ID;                 /* 0x80030000 */
40
  rtems_unsigned32 PCI_CSR;                /* 0x80030004 */
41
  rtems_unsigned32 PCI_CLASS;              /* 0x80030008 */
42
  rtems_unsigned32 PCI_MISC0;              /* 0x8003000C */
43
  rtems_unsigned32 PCI_BS;                 /* 0x80030010 */
44
  rtems_unsigned32 Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
45
  rtems_unsigned32 PCI_MISC1;              /* 0x8003003C */
46
  rtems_unsigned32 Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
47
  rtems_unsigned32 LSI0_CTL;               /* 0x80030100 */
48
  rtems_unsigned32 LSI0_BS;                /* 0x80030104 */
49
  rtems_unsigned32 LSI0_BD;                /* 0x80030108 */
50
  rtems_unsigned32 LSI0_TO;                /* 0x8003010C */
51
  rtems_unsigned32 Buf_0x80030110;         /* 0x80030110 */
52
  rtems_unsigned32 LSI1_CTL;               /* 0x80030114 */
53
  rtems_unsigned32 LSI1_BS;                /* 0x80030118 */
54
  rtems_unsigned32 LSI1_BD;                /* 0x8003011C */
55
  rtems_unsigned32 LSI1_TO;                /* 0x80030120 */
56
  rtems_unsigned32 Buf_0x80030124;         /* 0x80030124 */
57
  rtems_unsigned32 LSI2_CTL;               /* 0x80030128 */
58
  rtems_unsigned32 LSI2_BS;                /* 0x8003012C */
59
  rtems_unsigned32 LSI2_BD;                /* 0x80030130 */
60
  rtems_unsigned32 LSI2_TO;                /* 0x80030134 */
61
  rtems_unsigned32 Buf_0x80030138;         /* 0x80030138 */
62
  rtems_unsigned32 LSI3_CTL;               /* 0x8003013C */
63
  rtems_unsigned32 LSI3_BS;                /* 0x80030140 */
64
  rtems_unsigned32 LSI3_BD;                /* 0x80030144 */
65
  rtems_unsigned32 LSI3_TO;                /* 0x80030148 */
66
  rtems_unsigned32 Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
67
  rtems_unsigned32 SCYC_CTL;               /* 0x80030170 */
68
  rtems_unsigned32 SCYC_ADDR;              /* 0x80030174 */
69
  rtems_unsigned32 SCYC_EN;                /* 0x80030178 */
70
  rtems_unsigned32 SCYC_CMP;               /* 0x8003017C */
71
  rtems_unsigned32 SCYC_SWP;               /* 0x80030180 */
72
  rtems_unsigned32 LMISC;                  /* 0x80030184 */
73
  rtems_unsigned32 SLSI;                   /* 0x80030188 */
74
  rtems_unsigned32 L_CMDERR;               /* 0x8003018C */
75
  rtems_unsigned32 LAERR;                  /* 0x80030190 */
76
  rtems_unsigned32 Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
77
  rtems_unsigned32 DCTL;                   /* 0x80030200 */
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  rtems_unsigned32 DTBC;                   /* 0x80030204 */
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  rtems_unsigned32 DLA;                    /* 0x80030208 */
80
  rtems_unsigned32 Buf_0x8003020C;         /* 0x8003020C */
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  rtems_unsigned32 DVA;                    /* 0x80030210 */
82
  rtems_unsigned32 Buf_0x80030214;         /* 0x80030214 */
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  rtems_unsigned32 DCPP;                   /* 0x80030218 */
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  rtems_unsigned32 Buf_0x8003021C;         /* 0x8003021C */
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  rtems_unsigned32 DGCS;                   /* 0x80030220 */
86
  rtems_unsigned32 D_LLUE;                 /* 0x80030224 */
87
  rtems_unsigned32 Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
88
  rtems_unsigned32 LINT_EN;                /* 0x80030300 */
89
  rtems_unsigned32 LINT_STAT;              /* 0x80030304 */
90
  rtems_unsigned32 LINT_MAP0;              /* 0x80030308 */
91
  rtems_unsigned32 LINT_MAP1;              /* 0x8003030C */
92
  rtems_unsigned32 VINT_EN;                /* 0x80030310 */
93
  rtems_unsigned32 VINT_STAT;              /* 0x80030314 */
94
  rtems_unsigned32 VINT_MAP0;              /* 0x80030318 */
95
  rtems_unsigned32 VINT_MAP1;              /* 0x8003031C */
96
  rtems_unsigned32 STATID;                 /* 0x80030320 */
97
  rtems_unsigned32 V1_STATID;              /* 0x80030324 */
98
  rtems_unsigned32 V2_STATID;              /* 0x80030328 */
99
  rtems_unsigned32 V3_STATID;              /* 0x8003032C */
100
  rtems_unsigned32 V4_STATID;              /* 0x80030330 */
101
  rtems_unsigned32 V5_STATID;              /* 0x80030334 */
102
  rtems_unsigned32 V6_STATID;              /* 0x80030338 */
103
  rtems_unsigned32 V7_STATID;              /* 0x8003033C */
104
  rtems_unsigned32 Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
105
  rtems_unsigned32 MAST_CTL;               /* 0x80030400 */
106
  rtems_unsigned32 MISC_CTL;               /* 0x80030404 */
107
  rtems_unsigned32 MISC_STAT;              /* 0x80030408 */
108
  rtems_unsigned32 USER_AM;                /* 0x8003040C */
109
  rtems_unsigned32 Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
110
  rtems_unsigned32 VSI0_CTL;               /* 0x80030F00 */
111
  rtems_unsigned32 VSI0_BS;                /* 0x80030F04 */
112
  rtems_unsigned32 VSI0_BD;                /* 0x80030F08 */
113
  rtems_unsigned32 VSI0_TO;                /* 0x80030F0C */
114
  rtems_unsigned32 Buf_0x80030f10;         /* 0x80030F10 */
115
  rtems_unsigned32 VSI1_CTL;               /* 0x80030F14 */
116
  rtems_unsigned32 VSI1_BS;                /* 0x80030F18 */
117
  rtems_unsigned32 VSI1_BD;                /* 0x80030F1C */
118
  rtems_unsigned32 VSI1_TO;                /* 0x80030F20 */
119
  rtems_unsigned32 Buf_0x80030F24;         /* 0x80030F24 */
120
  rtems_unsigned32 VSI2_CTL;               /* 0x80030F28 */
121
  rtems_unsigned32 VSI2_BS;                /* 0x80030F2C */
122
  rtems_unsigned32 VSI2_BD;                /* 0x80030F30 */
123
  rtems_unsigned32 VSI2_TO;                /* 0x80030F34 */
124
  rtems_unsigned32 Buf_0x80030F38;         /* 0x80030F38 */
125
  rtems_unsigned32 VSI3_CTL;               /* 0x80030F3C */
126
  rtems_unsigned32 VSI3_BS;                /* 0x80030F40 */
127
  rtems_unsigned32 VSI3_BD;                /* 0x80030F44 */
128
  rtems_unsigned32 VSI3_TO;                /* 0x80030F48 */
129
  rtems_unsigned32 Buf_0x80030F4C[ 0x9 ];  /* 0x80030F4C */
130
  rtems_unsigned32 VRAI_CTL;               /* 0x80030F70 */
131
  rtems_unsigned32 VRAI_BS;                /* 0x80030F74 */
132
  rtems_unsigned32 Buf_0x80030F78[ 0x2 ];  /* 0x80030F78 */
133
  rtems_unsigned32 VCSR_CTL;               /* 0x80030F80 */
134
  rtems_unsigned32 VCSR_TO;                /* 0x80030F84 */
135
  rtems_unsigned32 V_AMERR;                /* 0x80030F88 */
136
  rtems_unsigned32 VAERR;                  /* 0x80030F8C */
137
  rtems_unsigned32 Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
138
  rtems_unsigned32 VCSR_CLR;               /* 0x80030FF4 */
139
  rtems_unsigned32 VCSR_SET;               /* 0x80030FF8 */
140
  rtems_unsigned32 VCSR_BS;                /* 0x80030FFC */
141
} Universe_Memory;
142
 
143
volatile Universe_Memory *UNIVERSE =
144
                         (volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
145
 
146
 
147
/********************************************************************
148
 ********************************************************************
149
 *********                                                  *********
150
 *********                                                  *********
151
 *********                                                  *********
152
 ********************************************************************
153
 ********************************************************************/
154
 
155
/*
156
 * Initializes the UNIVERSE chip.  This routine is called automatically
157
 * by the boot code.  This routine should be called by user code only if
158
 * a complete SCORE603e VME initialization is required.
159
 */
160
 
161
void initialize_universe()
162
{
163
  rtems_unsigned32 jumper_selection;
164
  rtems_unsigned32 pci_id;
165
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
166
  volatile rtems_unsigned32 universe_temp_value;
167
#endif
168
 
169
  /*
170
   * Read the VME jumper location to determine the VME base address
171
   */
172
  jumper_selection = PCI_bus_read(
173
                     (volatile rtems_unsigned32 *)SCORE603E_VME_JUMPER_ADDR );
174
  jumper_selection = (jumper_selection >> 3) & 0x1f;
175
 
176
  /*
177
   * Verify the UNIVERSE CHIP ID
178
   */
179
   pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
180
 
181
   /*
182
    * compare to known ID
183
    */
184
   if (pci_id !=  SCORE603E_UNIVERSE_CHIP_ID ){
185
     DEBUG_puts ("Invalid SCORE603E_UNIVERSE_CHIP_ID: ");
186
     rtems_fatal_error_occurred( 0x603e0bad );
187
   }
188
 
189
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
190
 
191
   /*
192
    * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
193
    * to specifies the 64 Kbyte aligned base address of the UNIVERSE register
194
    * space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
195
    */
196
   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
197
 
198
   /*
199
    * Set the UNIVERSE PCI Configuration Space Control and Status Register to
200
    * medium speed device, Target Back to Back Capable, Master Enable, Target
201
    * Memory Enable and Target IO Enable
202
    */
203
   Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
204
 
205
   /*
206
    * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
207
    */
208
   PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
209
 
210
   /*
211
    * Set the VMEbus Master Control register with retry forever, 256 bytes
212
    * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
213
    * aligned burst size and PCI bus number to be zero
214
    */
215
   PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
216
 
217
   /*
218
    * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
219
    * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
220
    * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
221
    PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
222
    */
223
 
224
   PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
225
   PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
226
   PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
227
   PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
228
 
229
   /*
230
    * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
231
    * BI-Mode VMEbus accesses can be made.
232
    */
233
 
234
   universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
235
 
236
   if (universe_temp_value & 0x100000)
237
     PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
238
 
239
#elif (SCORE603E_USE_DINK)
240
   /*
241
    * Do not modify the DINK setup of the universe chip.
242
    */
243
 
244
#else
245
#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
246
#endif
247
 
248
}
249
 
250
 
251
/*
252
 * Set the slave VME base address to the specified base address.
253
 * Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
254
 *       Slave Image 0 registers.
255
 */
256
void set_vme_base_address (
257
  rtems_unsigned32 base_address
258
)
259
{
260
  volatile rtems_unsigned32 temp;
261
 
262
  /*
263
   * Calculate the current size of the Slave VME image 0
264
   */
265
  temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
266
          ( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
267
 
268
  /*
269
   * Set the VMEbus Slave Image 0 Base Address to be
270
   * the specifed base address on VSI0_BS register.
271
   */
272
   PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
273
 
274
  /*
275
   * Update the VMEbus Slave Image 0 Bound Address.
276
   */
277
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
278
 
279
  /*
280
   * Update the VMEbus Slave Image 0 Translation Offset
281
   */
282
  temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
283
  PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
284
}
285
 
286
/*
287
 * Gets the VME base address
288
 */
289
rtems_unsigned32 get_vme_base_address ()
290
{
291
  volatile rtems_unsigned32 temp;
292
 
293
  temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
294
  temp &= 0xFFFFF000;
295
  return (temp);
296
}
297
 
298
rtems_unsigned32 get_vme_slave_size()
299
{
300
  volatile rtems_unsigned32 temp;
301
  temp  =  PCI_bus_read( &UNIVERSE->VSI0_BD);
302
  temp &= 0xFFFFF000;
303
  temp  = temp - get_vme_base_address ();
304
  return temp;
305
}
306
 
307
/*
308
 * Set the size of the VME slave image
309
 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
310
 */
311
void set_vme_slave_size (rtems_unsigned32 size)
312
{
313
  volatile rtems_unsigned32 temp;
314
 
315
  if (size<0)
316
    size = 0;
317
 
318
  if (size > 0x17FFFFF)
319
    size = 0x17FFFFF;
320
 
321
  /*
322
   * Read the VME slave image base address
323
   */
324
  temp = get_vme_base_address ();
325
 
326
  /*
327
   * Update the VMEbus Slave Image 0 Bound Address.
328
   */
329
  temp = temp + (size & 0xFFFFF000);
330
  PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
331
}
332
 

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