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#
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#  $Id: README,v 1.2 2001-09-27 12:01:03 chris Exp $
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#
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BSP NAME:           score603e
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BOARD:              VISTA SCORE 603e Generation I and II
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BUS:                N/A
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CPU FAMILY:         ppc
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CPU:                PowerPC 603e
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COPROCESSORS:       N/A
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MODE:               32 bit mode
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DEBUG MONITOR:      see note.
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PERIPHERALS
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===========
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TIMERS:             PPC internal Timebase register
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  RESOLUTION:
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SERIAL PORTS:       2 Z85C30s
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REAL-TIME CLOCK:    Generation  I: SGSM48T18
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                    Generation II: ICM7170AIBG
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DMA:                none
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VIDEO:              none
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SCSI:               none
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NETWORKING:         none
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DRIVER INFORMATION
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==================
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CLOCK DRIVER:       PPC internal
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IOSUPP DRIVER:      N/A
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SHMSUPP:            N/A
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TIMER DRIVER:       PPC internal
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TTY DRIVER:         PPC internal
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STDIO
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=====
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PORT:               Console port 0
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ELECTRICAL:         na
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BAUD:               9600
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BITS PER CHARACTER: 8
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PARITY:             n
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STOP BITS:          1
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Notes
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=====
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This BSP has been tested using any Rom monitor.  There have
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been three rom chips loaded on the boards.  One with the SDS
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debug monitor, one with the firmworks monitor, and one with
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the OAR Boot chip.  The OAR Boot chip contains the basic
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initialization from the SDS debugger and a jump to flash
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location 0x04001200.
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The compiler option SCORE603E_GENERATION is set to 1 or 2,
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for the generation to be produced.

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