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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [score603e/] [include/] [bsp.h] - Blame information for rev 623

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1 30 unneback 
/*  bsp.h
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 *
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 *  This include file contains all board IO definitions.
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 *
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 *  COPYRIGHT (c) 1989-1997.
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 *  On-Line Applications Research Corporation (OAR).
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 *  Copyright assigned to U.S. Government, 1994.
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 *
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 *  The license and distribution terms for this file may in
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 *  the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: bsp.h,v 1.2 2001-09-27 12:01:03 chris Exp $
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 */
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#ifndef __BSP_h
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#define __BSP_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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 *  confdefs.h overrides for this BSP:
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 *   - termios serial ports (defaults to 1)
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 *   - Interrupt stack space is not minimum if defined.
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 */
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#if (HAS_PMC_PSC8)
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#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
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#else
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#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
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#endif
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#define CONFIGURE_INTERRUPT_STACK_MEMORY  (12 * 1024)
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#ifdef ASM
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/* Definition of where to store registers in alignment handler */
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#define ALIGN_REGS 0x0140
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#else
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#include <rtems.h>
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#include <console.h>
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#include <clockdrv.h>
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#include <iosupp.h>
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#if (SCORE603E_GENERATION == 1)
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#include <gen1.h>
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#elif (SCORE603E_GENERATION == 2)
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#include <gen2.h>
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#else
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#error "Unknown Generation of  Score603e"
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#endif
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/*
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 * The following macro calculates the Baud constant. For the Z8530 chip.
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 *
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 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
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 *       for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2
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 */
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#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate  )   \
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  ( (_frequency /( _clock_by * 2 * _baud_rate))  - 2)
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#define Score603e_Z8530_Chip1_Baud( _value ) \
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  _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \
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     SCORE603E_85C30_1_CLOCK_X, _value )
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#define Score603e_Z8530_Chip0_Baud( _value ) \
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  _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \
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     SCORE603E_85C30_0_CLOCK_X, _value )
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#define Initialize_Board_ctrl_register()                         \
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  *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG |       \
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                               SCORE603E_BRD_FLASH_DISABLE_MASK) \
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/*
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 *  Define the time limits for RTEMS Test Suite test durations.
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 *  Long test and short test duration limits are provided.  These
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 *  values are in seconds and need to be converted to ticks for the
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 *  application.
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 *
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 */
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#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
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#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
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/*
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 *  Stuff for Time Test 27
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 */
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#define MUST_WAIT_FOR_INTERRUPT 1
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#define Install_tm27_vector( _handler ) \
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  set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
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#define Cause_tm27_intr()  \
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  do { \
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    unsigned32 _clicks = 8; \
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    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
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  } while (0)
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#define Clear_tm27_intr() \
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  do { \
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    unsigned32 _clicks = 0xffffffff; \
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    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
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  } while (0)
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#define Lower_tm27_intr() \
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  do { \
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    unsigned32 _msr = 0; \
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    _ISR_Set_level( 0 ); \
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    asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
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    _msr |=  0x8002; \
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    asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
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  } while (0)
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/* Constants */
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/*
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 *  Device Driver Table Entries
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 */
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/*
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 * NOTE: Use the standard Console driver entry
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 */
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/*
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 * NOTE: Use the standard Clock driver entry
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 */
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/*
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 *  Information placed in the linkcmds file.
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 */
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extern int   RAM_START;
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extern int   RAM_END;
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extern int   RAM_SIZE;
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extern int   PROM_START;
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extern int   PROM_END;
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extern int   PROM_SIZE;
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extern int   CLOCK_SPEED;
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extern int   CPU_PPC_CLICKS_PER_MS;
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extern int   end;        /* last address in the program */
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/*
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 * How many libio files we want
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 */
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#define BSP_LIBIO_MAX_FDS       20
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/* functions */
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void bsp_start( void );
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void bsp_cleanup( void );
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rtems_isr_entry set_vector(                    /* returns old vector */
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  rtems_isr_entry     handler,                  /* isr routine        */
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  rtems_vector_number vector,                   /* vector number      */
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  int                 type                      /* RTEMS or RAW intr  */
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);
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/*
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 * spurious.c
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 */
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rtems_isr bsp_stub_handler(
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   rtems_vector_number trap
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);
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rtems_isr bsp_spurious_handler(
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   rtems_vector_number trap
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);
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void bsp_spurious_initialize();
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/*
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 * genvec.c
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 */
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rtems_isr_entry  set_EE_vector(
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  rtems_isr_entry     handler,                  /* isr routine        */
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  rtems_vector_number vector                    /* vector number      */
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);
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void initialize_external_exception_vector ();
189 
 
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/*
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 * console.c
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 */
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void DEBUG_puts( char *string );
194 
 
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void BSP_fatal_return( void );
196 
 
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/*
198 
 * Hwr_init.c
199 
 */
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void init_PCI();
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void instruction_cache_enable ();
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void data_cache_enable ();
203 
 
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void initialize_PCI_bridge ();
206 
rtems_unsigned16 read_and_clear_irq ();
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void set_irq_mask(
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  rtems_unsigned16 value
209 
);
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rtems_unsigned16 get_irq_mask();
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/*
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 * universe.c
214 
 */
215 
void initialize_universe();
216 
 
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void set_irq_mask(
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  rtems_unsigned16 value
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);
220 
 
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rtems_unsigned16 get_irq_mask();
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void unmask_irq(
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  rtems_unsigned16 irq_idx
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);
226 
 
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void init_irq_data_register();
228 
 
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rtems_unsigned16 read_and_clear_PMC_irq(
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  rtems_unsigned16    irq
231 
);
232 
 
233 
rtems_boolean Is_PMC_IRQ(
234 
  rtems_unsigned32   pmc_irq,
235 
  rtems_unsigned16   status_word
236 
);
237 
 
238 
rtems_unsigned16 read_and_clear_irq();
239 
 
240 
/*
241 
 * FPGA.c
242 
 */
243 
void initialize_PCI_bridge ();
244 
 
245 
/* flash.c */
246 
 
247 
unsigned int SCORE603e_FLASH_Disable(
248 
  rtems_unsigned32               unused
249 
);
250 
unsigned int SCORE603e_FLASH_verify_enable();
251 
unsigned int SCORE603e_FLASH_Enable_writes(
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  rtems_unsigned32               area        /* Unused  */
253 
);
254 
 
255 
#define Convert_Endian_32( _data ) \
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  ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) |  \
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    ((_data&0x00ff0000)>>8)  | ((_data&0xff000000)>>24) )
258 
 
259 
#define Convert_Endian_16( _data ) \
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  ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) )
261 
 
262 
extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
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extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
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extern rtems_unsigned32          bsp_isr_level;
265 
 
266 
#endif /* ASM */
267 
 
268 
#ifdef __cplusplus
269 
}
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#endif
271 
 
272 
#endif
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/* end of include file */
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