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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [score603e/] [startup/] [82378zb.c] - Blame information for rev 173

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/*  82378zb.c
 *
 *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *  Copyright assigned to U.S. Government, 1994.
 *
 *  The license and distribution terms for this file may in
 *  the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id:
 */
 
#include <bsp.h>
#if (SCORE603E_GENERATION == 1)
#include <rtems/libio.h>
 
#include <libcsupport.h>
 
#include <string.h>
#include <fcntl.h>
#include <assert.h>
/*
 * initialize 82378zb
 */
void initialize_PCI_bridge ()
{
 
  /*
   * INT CNTRL-1 ICW1
   *            LTIM and ICW4
   */
  Write_82378ZB( 0x20, 0x19);
 
  /*
   * INT CNTRL-1 ICW 2
   *     Sets 5 msbs of the base address in the interrupt vector table
   *     for the vector  routines to  0100 0 ??
   */
  Write_82378ZB( 0x21, 0x40 );
 
  /*
   * INT CNTRL-1 ICW 3
   *     Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
   */
  Write_82378ZB( 0x21, 0x04 );
 
  /*
   * INT CNTRL-1 ICW 4
   *     Set Microprocessor mode for 80x86 system.
   */
  Write_82378ZB( 0x21, 0x01 );
 
  /*
   * INT CNTRL-1 OCW 2
   *     Set Non-specific EOI command
   */
  Write_82378ZB( 0x20, 0x20 );
 
  /*
   * INT CNTRL-1 OCW 3
   *     Interrupt controller in normal mask mode.
   *     Disable Poll mode command
   *     Read IRQ register.
   */
  Write_82378ZB( 0x20, 0x2a );
 
  /*
   * INT CNTRL-1 OCW 1
   *     Write Interrupt Request mask for IRQ[7:0].  An interrupt request for
   *     a masked IRQ will not set the interrupt request register (IRR) bit for
   *     that channel.
   *
   *     XXXX - Was 0xfd Only allowing Timer interrupt through changed to
   *            0xe1.
   */
  Write_82378ZB( 0x21, 0xe1 );
 
  /*
   * INT CNTRL-2 ICW 1
   *            LTIM and ICW4
   */
  Write_82378ZB( 0xa0, 0x19 );
 
  /*
   * INT CNTRL-2 ICW 2
   *     Sets 5 msbs of the base address in the interrupt vector table
   *     for the vector  routines to  0100 1 ??
   */
  Write_82378ZB( 0xa1, 0x48 );
 
  /*
   * INT CNTRL-1 ICW 3
   *     Slave Identification Code (Must be intialized to 2).
   */
  Write_82378ZB( 0xa1, 0x02 );
 
  /*
   * INT CNTRL-1 ICW 4
   *     Set Microprocessor mode for 80x86 system.
   */
  Write_82378ZB( 0xa1, 0x01 );
 
  /*
   * INT CNTRL-1 OCW 2
   *     Set Non-specific EOI command
   */
  Write_82378ZB( 0xa0, 0x20 );
 
  /*
   * INT CNTRL-1 OCW 3
   *     Interrupt controller in normal mask mode.
   *     Disable Poll mode command
   *     Read IRQ register.
   */
  Write_82378ZB( 0xa0, 0x2a );
 
  /*
   * INT CNTRL-1 OCW 1
   *     Write Interrupt Request mask for IRQ[7:0].  An interrupt request for
   *     a masked IRQ will not set the interrupt request register (IRR) bit for
   *     that channel.
   *
   *     XXXX - All interrupts masked.
   */
  Write_82378ZB( 0xa1, 0xff );
}
 
 
rtems_unsigned16 read_and_clear_irq ()
{
  rtems_unsigned16 irq;
 
  /*
   * XXX - Fix this for all interrupts later
   */
 
  Write_82378ZB( 0x20, 0x0c);
  Read_82378ZB( 0x20, irq );
  irq &= 0x7;
  Write_82378ZB( 0x20, 0x20 );
 
  return irq;
}
 
void init_irq_data_register()
{
  assert (0);
}
rtems_unsigned16 get_irq_mask()
{
  assert (0);
  return 0;
}
void set_irq_mask(
  rtems_unsigned16 value
)
{
  assert (0);
}
#endif /* end of generation 1 */

Line No.	Rev	Author	Line
1	30	unneback	`/* 82378zb.c`
2			`*`
3			`* COPYRIGHT (c) 1989-1997.`
4			`* On-Line Applications Research Corporation (OAR).`
5			`* Copyright assigned to U.S. Government, 1994.`
6			`*`
7			`* The license and distribution terms for this file may in`
8			`* the file LICENSE in this distribution or at`
9			`* http://www.OARcorp.com/rtems/license.html.`
10			`*`
11			`* $Id:`
12			`*/`
13
14			`#include <bsp.h>`
15			`#if (SCORE603E_GENERATION == 1)`
16			`#include <rtems/libio.h>`
17
18			`#include <libcsupport.h>`
19
20			`#include <string.h>`
21			`#include <fcntl.h>`
22			`#include <assert.h>`
23			`/*`
24			`* initialize 82378zb`
25			`*/`
26			`void initialize_PCI_bridge ()`
27			`{`
28
29			`/*`
30			`* INT CNTRL-1 ICW1`
31			`* LTIM and ICW4`
32			`*/`
33			`Write_82378ZB( 0x20, 0x19);`
34
35			`/*`
36			`* INT CNTRL-1 ICW 2`
37			`* Sets 5 msbs of the base address in the interrupt vector table`
38			`* for the vector routines to 0100 0 ??`
39			`*/`
40			`Write_82378ZB( 0x21, 0x40 );`
41
42			`/*`
43			`* INT CNTRL-1 ICW 3`
44			`* Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1`
45			`*/`
46			`Write_82378ZB( 0x21, 0x04 );`
47
48			`/*`
49			`* INT CNTRL-1 ICW 4`
50			`* Set Microprocessor mode for 80x86 system.`
51			`*/`
52			`Write_82378ZB( 0x21, 0x01 );`
53
54			`/*`
55			`* INT CNTRL-1 OCW 2`
56			`* Set Non-specific EOI command`
57			`*/`
58			`Write_82378ZB( 0x20, 0x20 );`
59
60			`/*`
61			`* INT CNTRL-1 OCW 3`
62			`* Interrupt controller in normal mask mode.`
63			`* Disable Poll mode command`
64			`* Read IRQ register.`
65			`*/`
66			`Write_82378ZB( 0x20, 0x2a );`
67
68			`/*`
69			`* INT CNTRL-1 OCW 1`
70			`* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for`
71			`* a masked IRQ will not set the interrupt request register (IRR) bit for`
72			`* that channel.`
73			`*`
74			`* XXXX - Was 0xfd Only allowing Timer interrupt through changed to`
75			`* 0xe1.`
76			`*/`
77			`Write_82378ZB( 0x21, 0xe1 );`
78
79			`/*`
80			`* INT CNTRL-2 ICW 1`
81			`* LTIM and ICW4`
82			`*/`
83			`Write_82378ZB( 0xa0, 0x19 );`
84
85			`/*`
86			`* INT CNTRL-2 ICW 2`
87			`* Sets 5 msbs of the base address in the interrupt vector table`
88			`* for the vector routines to 0100 1 ??`
89			`*/`
90			`Write_82378ZB( 0xa1, 0x48 );`
91
92			`/*`
93			`* INT CNTRL-1 ICW 3`
94			`* Slave Identification Code (Must be intialized to 2).`
95			`*/`
96			`Write_82378ZB( 0xa1, 0x02 );`
97
98			`/*`
99			`* INT CNTRL-1 ICW 4`
100			`* Set Microprocessor mode for 80x86 system.`
101			`*/`
102			`Write_82378ZB( 0xa1, 0x01 );`
103
104			`/*`
105			`* INT CNTRL-1 OCW 2`
106			`* Set Non-specific EOI command`
107			`*/`
108			`Write_82378ZB( 0xa0, 0x20 );`
109
110			`/*`
111			`* INT CNTRL-1 OCW 3`
112			`* Interrupt controller in normal mask mode.`
113			`* Disable Poll mode command`
114			`* Read IRQ register.`
115			`*/`
116			`Write_82378ZB( 0xa0, 0x2a );`
117
118			`/*`
119			`* INT CNTRL-1 OCW 1`
120			`* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for`
121			`* a masked IRQ will not set the interrupt request register (IRR) bit for`
122			`* that channel.`
123			`*`
124			`* XXXX - All interrupts masked.`
125			`*/`
126			`Write_82378ZB( 0xa1, 0xff );`
127			`}`
128
129
130			`rtems_unsigned16 read_and_clear_irq ()`
131			`{`
132			`rtems_unsigned16 irq;`
133
134			`/*`
135			`* XXX - Fix this for all interrupts later`
136			`*/`
137
138			`Write_82378ZB( 0x20, 0x0c);`
139			`Read_82378ZB( 0x20, irq );`
140			`irq &= 0x7;`
141			`Write_82378ZB( 0x20, 0x20 );`
142
143			`return irq;`
144			`}`
145
146			`void init_irq_data_register()`
147			`{`
148			`assert (0);`
149			`}`
150			`rtems_unsigned16 get_irq_mask()`
151			`{`
152			`assert (0);`
153			`return 0;`
154			`}`
155			`void set_irq_mask(`
156			`rtems_unsigned16 value`
157			`)`
158			`{`
159			`assert (0);`
160			`}`
161			`#endif /* end of generation 1 */`

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [score603e/] [startup/] [82378zb.c] - Blame information for rev 173