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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [shared/] [irq/] [i8259.c] - Blame information for rev 543

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1 30 unneback 
 
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/*
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 *  This file contains the implementation of the function described in irq.h
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 *  related to Intel 8259 Programmable Interrupt controller.
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 *
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 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
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 *
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 *  The license and distribution terms for this file may be
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 *  found in found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: i8259.c,v 1.2 2001-09-27 12:01:06 chris Exp $
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 */
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#include <bsp.h>
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#include <bsp/irq.h>
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/*-------------------------------------------------------------------------+
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| Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.
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+--------------------------------------------------------------------------*/
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/*
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 * lower byte is interrupt mask on the master PIC.
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 * while upper bits are interrupt on the slave PIC.
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 */
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volatile rtems_i8259_masks i8259s_cache = 0xfffb;
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/*-------------------------------------------------------------------------+
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|         Function:  BSP_irq_disable_at_i8259s
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|      Description: Mask IRQ line in appropriate PIC chip.
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| Global Variables: i8259s_cache
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|        Arguments: vector_offset - number of IRQ line to mask.
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|          Returns: Nothing.
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+--------------------------------------------------------------------------*/
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int BSP_irq_disable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
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{
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  unsigned short mask;
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  unsigned int  level;
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  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
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       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
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       )
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    return 1;
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  _CPU_ISR_Disable(level);
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  mask = 1 << irqLine;
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  i8259s_cache |= mask;
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  if (irqLine < 8)
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  {
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    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
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  }
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  else
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  {
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    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
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  }
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  _CPU_ISR_Enable (level);
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  return 0;
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}
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/*-------------------------------------------------------------------------+
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|         Function:  BSP_irq_enable_at_i8259s
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|      Description: Unmask IRQ line in appropriate PIC chip.
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| Global Variables: i8259s_cache
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|        Arguments: irqLine - number of IRQ line to mask.
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|          Returns: Nothing.
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+--------------------------------------------------------------------------*/
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int BSP_irq_enable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
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{
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  unsigned short mask;
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  unsigned int  level;
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  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
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       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET )
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       )
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    return 1;
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  _CPU_ISR_Disable(level);
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  mask = ~(1 << irqLine);
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  i8259s_cache &= mask;
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  if (irqLine < 8)
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  {
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    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
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  }
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  else
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  {
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    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
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  }
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  _CPU_ISR_Enable (level);
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  return 0;
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} /* mask_irq */
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int BSP_irq_enabled_at_i8259s           (const rtems_irq_symbolic_name irqLine)
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{
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  unsigned short mask;
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  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
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       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
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     )
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    return 1;
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  mask = (1 << irqLine);
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  return  (~(i8259s_cache & mask));
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}
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/*-------------------------------------------------------------------------+
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|         Function: BSP_irq_ack_at_i8259s
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|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
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| Global Variables: None.
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|        Arguments: irqLine - number of IRQ line to acknowledge.
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|          Returns: Nothing.
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+--------------------------------------------------------------------------*/
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int BSP_irq_ack_at_i8259s       (const rtems_irq_symbolic_name irqLine)
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{
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  if (irqLine >= 8) {
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    outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI);
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    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8)));
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  }
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  else {
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    outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine));
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  }
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  return 0;
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} /* ackIRQ */
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void BSP_i8259s_init(void)
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{
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  /*
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   * init master 8259 interrupt controller
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   */
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  outport_byte(PIC_MASTER_COMMAND_IO_PORT, 0x11); /* Start init sequence */
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  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x00);/* Vector base  = 0 */
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  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x04);/* edge tiggered, Cascade (slave) on IRQ2 */
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  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x01);/* Select 8086 mode */
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  outport_byte(PIC_MASTER_IMR_IO_PORT, 0xFB); /* Mask all except cascade */
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  /*
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   * init slave  interrupt controller
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   */
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  outport_byte(PIC_SLAVE_COMMAND_IO_PORT, 0x11); /* Start init sequence */
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  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x08);/* Vector base  = 8 */
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  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x02);/* edge triggered, Cascade (slave) on IRQ2 */
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  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */
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  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
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}
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