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unneback |
/*
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* This file contains the assembly code for the PowerPC
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* IRQ veneers for RTEMS.
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Modified to support the MCP750.
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* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
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*
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*
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* $Id: irq_asm.S,v 1.2 2001-09-27 12:01:06 chris Exp $
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*/
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#include
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#include
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#include
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#include
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#include "asm.h"
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#define SYNC \
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sync; \
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isync
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.text
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.p2align 5
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PUBLIC_VAR(decrementer_exception_vector_prolog_code)
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SYM (decrementer_exception_vector_prolog_code):
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/*
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* let room for exception frame
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*/
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stwu r1, - (EXCEPTION_FRAME_END)(r1)
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stw r4, GPR4_OFFSET(r1)
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li r4, ASM_DEC_VECTOR
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ba shared_raw_irq_code_entry
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PUBLIC_VAR (decrementer_exception_vector_prolog_code_size)
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decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
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PUBLIC_VAR(external_exception_vector_prolog_code)
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SYM (external_exception_vector_prolog_code):
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/*
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* let room for exception frame
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*/
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stwu r1, - (EXCEPTION_FRAME_END)(r1)
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stw r4, GPR4_OFFSET(r1)
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li r4, ASM_EXT_VECTOR
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ba shared_raw_irq_code_entry
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PUBLIC_VAR (external_exception_vector_prolog_code_size)
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external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
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PUBLIC_VAR(shared_raw_irq_code_entry)
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PUBLIC_VAR(C_dispatch_irq_handler)
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.p2align 5
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SYM (shared_raw_irq_code_entry):
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/*
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* Entry conditions :
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* Registers already saved : R1, R4
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* R1 : points to a location with enough room for the
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* interrupt frame
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* R4 : vector number
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*/
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/*
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* Save SRR0/SRR1 As soon As possible as it is the minimal needed
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* to reenable exception processing
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*/
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stw r0, GPR0_OFFSET(r1)
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stw r2, GPR2_OFFSET(r1)
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stw r3, GPR3_OFFSET(r1)
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mfsrr0 r0
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mfsrr1 r2
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mfmsr r3
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stw r0, SRR0_FRAME_OFFSET(r1)
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stw r2, SRR1_FRAME_OFFSET(r1)
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/*
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* Enable data and instruction address translation, exception recovery
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*
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* also, on CPUs with FP, enable FP so that FP context can be
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* saved and restored (using FP instructions)
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*/
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#if (PPC_HAS_FPU == 0)
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ori r3, r3, MSR_RI | MSR_IR | MSR_DR
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#else
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ori r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
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#endif
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mtmsr r3
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SYNC
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/*
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* Push C scratch registers on the current stack. It may
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* actually be the thread stack or the interrupt stack.
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* Anyway we have to make it in order to be able to call C/C++
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* functions. Depending on the nesting interrupt level, we will
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* switch to the right stack later.
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*/
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stw r5, GPR5_OFFSET(r1)
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stw r6, GPR6_OFFSET(r1)
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stw r7, GPR7_OFFSET(r1)
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stw r8, GPR8_OFFSET(r1)
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stw r9, GPR9_OFFSET(r1)
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stw r10, GPR10_OFFSET(r1)
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stw r11, GPR11_OFFSET(r1)
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stw r12, GPR12_OFFSET(r1)
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stw r13, GPR13_OFFSET(r1)
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mfcr r5
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mfctr r6
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mfxer r7
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mflr r8
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stw r5, EXC_CR_OFFSET(r1)
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stw r6, EXC_CTR_OFFSET(r1)
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stw r7, EXC_XER_OFFSET(r1)
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stw r8, EXC_LR_OFFSET(r1)
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/*
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* Add some non volatile registers to store information
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* that will be used when returning from C handler
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*/
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stw r14, GPR14_OFFSET(r1)
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stw r15, GPR15_OFFSET(r1)
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/*
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* save current stack pointer location in R14
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*/
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addi r14, r1, 0
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/*
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* store part of _Thread_Dispatch_disable_level address in R15
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*/
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addis r15,0, _Thread_Dispatch_disable_level@ha
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/*
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* Get current nesting level in R2
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*/
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mfspr r2, SPRG0
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/*
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* Check if stack switch is necessary
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*/
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cmpwi r2,0
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bne nested
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mfspr r1, SPRG1
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nested:
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/*
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* Start Incrementing nesting level in R2
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*/
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addi r2,r2,1
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/*
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* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
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*/
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lwz r6,_Thread_Dispatch_disable_level@l(r15)
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/*
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* store new nesting level in SPRG0
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*/
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mtspr SPRG0, r2
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addi r6, r6, 1
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mfmsr r5
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/*
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* store new _Thread_Dispatch_disable_level value
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*/
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stw r6, _Thread_Dispatch_disable_level@l(r15)
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/*
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* We are now running on the interrupt stack. External and decrementer
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* exceptions are still disabled. I see no purpose trying to optimize
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* further assembler code.
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*/
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/*
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* Call C exception handler for decrementer Interrupt frame is passed just
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* in case...
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*/
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addi r3, r14, 0x8
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bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
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/*
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* start decrementing nesting level. Note : do not test result against 0
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* value as an easy exit condition because if interrupt nesting level > 1
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* then _Thread_Dispatch_disable_level > 1
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*/
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mfspr r2, SPRG0
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/*
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* start decrementing _Thread_Dispatch_disable_level
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*/
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lwz r3,_Thread_Dispatch_disable_level@l(r15)
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addi r2, r2, -1 /* Continue decrementing nesting level */
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addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
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mtspr SPRG0, r2 /* End decrementing nesting level */
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stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
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cmpwi r3, 0
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/*
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* switch back to original stack (done here just optimize registers
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* contention. Could have been done before...)
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*/
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addi r1, r14, 0
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bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
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/*
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* Here we are running again on the thread system stack.
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* We have interrupt nesting level = _Thread_Dispatch_disable_level = 0.
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* Interrupt are still disabled. Time to check if scheduler request to
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* do something with the current thread...
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*/
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addis r4, 0, _Context_Switch_necessary@ha
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lwz r5, _Context_Switch_necessary@l(r4)
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cmpwi r5, 0
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bne switch
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addis r6, 0, _ISR_Signals_to_thread_executing@ha
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lwz r7, _ISR_Signals_to_thread_executing@l(r6)
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cmpwi r7, 0
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li r8, 0
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beq easy_exit
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stw r8, _ISR_Signals_to_thread_executing@l(r6)
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/*
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* going to call _ThreadProcessSignalsFromIrq
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* Push a complete exception like frame...
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*/
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stmw r16, GPR16_OFFSET(r1)
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addi r3, r1, 0x8
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/*
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* compute SP at exception entry
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*/
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addi r2, r1, EXCEPTION_FRAME_END
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/*
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* store it at the right place
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*/
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stw r2, GPR1_OFFSET(r1)
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/*
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* Call High Level signal handling code
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*/
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bl _ThreadProcessSignalsFromIrq
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/*
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* start restoring exception like frame
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*/
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lwz r31, EXC_CTR_OFFSET(r1)
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lwz r30, EXC_XER_OFFSET(r1)
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lwz r29, EXC_CR_OFFSET(r1)
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lwz r28, EXC_LR_OFFSET(r1)
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mtctr r31
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mtxer r30
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mtcr r29
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mtlr r28
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lmw r4, GPR4_OFFSET(r1)
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lwz r2, GPR2_OFFSET(r1)
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lwz r0, GPR0_OFFSET(r1)
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/*
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* Disable data and instruction translation. Make path non recoverable...
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*/
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mfmsr r3
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xori r3, r3, MSR_RI | MSR_IR | MSR_DR
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mtmsr r3
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SYNC
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/*
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* Restore rfi related settings
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*/
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lwz r3, SRR1_FRAME_OFFSET(r1)
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mtsrr1 r3
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lwz r3, SRR0_FRAME_OFFSET(r1)
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mtsrr0 r3
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lwz r3, GPR3_OFFSET(r1)
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addi r1,r1, EXCEPTION_FRAME_END
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SYNC
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rfi
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| 275 |
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switch:
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bl SYM (_Thread_Dispatch)
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easy_exit:
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/*
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| 281 |
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* start restoring interrupt frame
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| 282 |
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*/
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| 283 |
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lwz r3, EXC_CTR_OFFSET(r1)
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lwz r4, EXC_XER_OFFSET(r1)
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| 285 |
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lwz r5, EXC_CR_OFFSET(r1)
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| 286 |
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lwz r6, EXC_LR_OFFSET(r1)
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| 287 |
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| 288 |
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mtctr r3
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mtxer r4
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mtcr r5
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| 291 |
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mtlr r6
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| 292 |
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| 293 |
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lwz r15, GPR15_OFFSET(r1)
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| 294 |
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lwz r14, GPR14_OFFSET(r1)
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| 295 |
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lwz r13, GPR13_OFFSET(r1)
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| 296 |
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lwz r12, GPR12_OFFSET(r1)
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| 297 |
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lwz r11, GPR11_OFFSET(r1)
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| 298 |
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lwz r10, GPR10_OFFSET(r1)
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| 299 |
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lwz r9, GPR9_OFFSET(r1)
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| 300 |
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lwz r8, GPR8_OFFSET(r1)
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| 301 |
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lwz r7, GPR7_OFFSET(r1)
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| 302 |
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lwz r6, GPR6_OFFSET(r1)
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| 303 |
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lwz r5, GPR5_OFFSET(r1)
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| 304 |
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| 305 |
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/*
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| 306 |
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* Disable nested exception processing, data and instruction
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| 307 |
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* translation.
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| 308 |
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*/
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| 309 |
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mfmsr r3
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| 310 |
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xori r3, r3, MSR_RI | MSR_IR | MSR_DR
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| 311 |
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mtmsr r3
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| 312 |
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SYNC
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| 313 |
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/*
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| 314 |
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* Restore rfi related settings
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| 315 |
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*/
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| 316 |
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| 317 |
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lwz r4, SRR1_FRAME_OFFSET(r1)
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| 318 |
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lwz r2, SRR0_FRAME_OFFSET(r1)
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| 319 |
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lwz r3, GPR3_OFFSET(r1)
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| 320 |
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lwz r0, GPR0_OFFSET(r1)
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| 321 |
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| 322 |
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mtsrr1 r4
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| 323 |
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mtsrr0 r2
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| 324 |
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lwz r4, GPR4_OFFSET(r1)
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| 325 |
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lwz r2, GPR2_OFFSET(r1)
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| 326 |
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addi r1,r1, EXCEPTION_FRAME_END
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| 327 |
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SYNC
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| 328 |
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rfi
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| 329 |
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