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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [shared/] [start/] [start.S] - Blame information for rev 562

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Line No. Rev Author Line
1 30 unneback
/*
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 *  start.S :     RTEMS entry point
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 *
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 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
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 *
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 *  The license and distribution terms for this file may be
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 *  found in found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: start.S,v 1.2 2001-09-27 12:01:07 chris Exp $
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 *
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 */
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#include 
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#include 
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#include 
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#include 
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#include "asm.h"
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#define SYNC \
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        sync; \
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        isync
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#define KERNELBASE      0x0
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#define MONITOR_ENTER                   \
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        mfmsr   r10             ;       \
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        ori     r10,r10,MSR_IP  ;       \
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        mtmsr   r10             ;       \
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        li      r10,0x63        ;       \
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        sc
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        .text
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        .globl  __rtems_entry_point
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        .type   __rtems_entry_point,@function
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__rtems_entry_point:
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#ifdef DEBUG_EARLY_START
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        MONITOR_ENTER
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#endif
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/*
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 * PREP
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 * This is jumped to on prep systems right after the kernel is relocated
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 * to its proper place in memory by the boot loader.  The expected layout
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 * of the regs is:
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 *   r3: ptr to residual data
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 *   r4: initrd_start or if no initrd then 0
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 *   r5: initrd_end - unused if r4 is 0
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 *   r6: Start of command line string
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 *   r7: End of command line string
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 *
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 *   The Prep boot loader insure that the MMU is currently off...
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 *
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 */
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        mr      r31,r3                  /* save parameters */
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        mr      r30,r4
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        mr      r29,r5
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        mr      r28,r6
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        mr      r27,r7
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        /*
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         * Make sure we have nothing in BATS and TLB
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         */
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        bl      clear_bats
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        bl      flush_tlbs
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/*
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 * Use the first pair of BAT registers to map the 1st 64MB
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 * of RAM to KERNELBASE.
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 */
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        lis     r11,KERNELBASE@h
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        ori     r11,r11,0x7fe           /* set up BAT registers for 604 */
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        li      r8,2                    /* R/W access */
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        isync
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        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
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        mtspr   DBAT0U,r11              /* bit in upper BAT register */
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        mtspr   IBAT0L,r8
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        mtspr   IBAT0U,r11
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        isync
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/*
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 * we now have the 1st 64M of ram mapped with the bats.
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 */
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enter_C_code:
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        bl      MMUon
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        /*
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         * stack = &__rtems_end + 4096
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         */
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        addis   r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha
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        addi    r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
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        mr      r1, r9
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        bl      zero_bss
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        /*
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         * restore prep boot params
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         */
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        mr      r3,r31
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        mr      r4,r30
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        mr      r5,r29
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        mr      r6,r28
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        mr      r7,r27
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        bl      save_boot_params
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        bl      boot_card
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        bl      _return_to_ppcbug
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        .globl  MMUon
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        .type   MMUon,@function
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MMUon:
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        mfmsr   r0
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#if (PPC_HAS_FPU == 0)
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        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
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        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
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#else
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        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
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        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
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#endif
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        mflr    r11
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        mtsrr0  r11
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        mtsrr1  r0
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        SYNC
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        rfi
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        .globl  MMUoff
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        .type   MMUoff,@function
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MMUoff:
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        mfmsr   r0
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        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
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        mflr    r11
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        xori    r0,r0,MSR_IR|MSR_DR
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        mtsrr0  r11
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        mtsrr1  r0
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        SYNC
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        rfi
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        .globl  _return_to_ppcbug
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        .type   _return_to_ppcbug,@function
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_return_to_ppcbug:
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        mflr    r30
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        bl      MMUoff
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        MONITOR_ENTER
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        bl      MMUon
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        mtctr   r30
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        bctr
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/*
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 * An undocumented "feature" of 604e requires that the v bit
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 * be cleared before changing BAT values.
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 *
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 * Also, newer IBM firmware does not clear bat3 and 4 so
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 * this makes sure it's done.
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 *  -- Cort
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 */
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clear_bats:
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        li      r20,0
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        mfspr   r9,PVR
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        rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
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        cmpwi   r9, 1
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        SYNC
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        beq     1f
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        mtspr   DBAT0U,r20
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        mtspr   DBAT0L,r20
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        mtspr   DBAT1U,r20
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        mtspr   DBAT1L,r20
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        mtspr   DBAT2U,r20
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        mtspr   DBAT2L,r20
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        mtspr   DBAT3U,r20
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        mtspr   DBAT3L,r20
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1:
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        mtspr   IBAT0U,r20
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        mtspr   IBAT0L,r20
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        mtspr   IBAT1U,r20
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        mtspr   IBAT1L,r20
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        mtspr   IBAT2U,r20
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        mtspr   IBAT2L,r20
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        mtspr   IBAT3U,r20
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        mtspr   IBAT3L,r20
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        SYNC
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        blr
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flush_tlbs:
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        lis     r20, 0x1000
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1:      addic.  r20, r20, -0x1000
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        tlbie   r20
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        blt     1b
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        sync
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        blr
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