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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [powerpc/] [shared/] [vectors/] [vectors.h] - Blame information for rev 593

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/*
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 * vectors.h Exception frame related contant and API.
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 *
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 *  This include file describe the data structure and the functions implemented
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 *  by rtems to handle exceptions.
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 *
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 *  CopyRight (C) 1999 valette@crf.canon.fr
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 *
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 *  The license and distribution terms for this file may be
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 *  found in found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: vectors.h,v 1.2 2001-09-27 12:01:09 chris Exp $
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 */
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#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
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#define LIBBSP_POWERPC_MCP750_VECTORS_H
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/*
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 * The callee (high level exception code written in C)
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 * will store the Link Registers (return address) at entry r1 + 4 !!!.
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 * So let room for it!!!.
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 */
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#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
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#define SRR0_FRAME_OFFSET 8
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#define SRR1_FRAME_OFFSET 12
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#define EXCEPTION_NUMBER_OFFSET 16
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#define GPR0_OFFSET 20
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#define GPR1_OFFSET 24
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#define GPR2_OFFSET 28
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#define GPR3_OFFSET 32
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#define GPR4_OFFSET 36
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#define GPR5_OFFSET 40
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#define GPR6_OFFSET 44
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#define GPR7_OFFSET 48
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#define GPR8_OFFSET 52
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#define GPR9_OFFSET 56
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#define GPR10_OFFSET 60
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#define GPR11_OFFSET 64
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#define GPR12_OFFSET 68
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#define GPR13_OFFSET 72
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#define GPR14_OFFSET 76
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#define GPR15_OFFSET 80
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#define GPR16_OFFSET 84
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#define GPR17_OFFSET 88
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#define GPR18_OFFSET 92
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#define GPR19_OFFSET 96
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#define GPR20_OFFSET 100
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#define GPR21_OFFSET 104
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#define GPR22_OFFSET 108
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#define GPR23_OFFSET 112
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#define GPR24_OFFSET 116
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#define GPR25_OFFSET 120
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#define GPR26_OFFSET 124
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#define GPR27_OFFSET 128
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#define GPR28_OFFSET 132
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#define GPR29_OFFSET 136
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#define GPR30_OFFSET 140
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#define GPR31_OFFSET 144
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#define EXC_CR_OFFSET 148
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#define EXC_CTR_OFFSET 152
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#define EXC_XER_OFFSET 156
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#define EXC_LR_OFFSET 160
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#define EXC_DAR_OFFSET 164
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/*
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 * maintain the EABI requested 8 bytes aligment
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 * As SVR4 ABI requires 16, make it 16 (as some
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 * exception may need more registers to be processed...)
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 */
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#define    EXCEPTION_FRAME_END 176
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#ifndef ASM
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/*
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 * default raw exception handlers
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 */
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extern  void default_exception_vector_code_prolog();
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extern  int  default_exception_vector_code_prolog_size;
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/* codemove is like memmove, but it also gets the cache line size
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 * as 4th parameter to synchronize them. If this last parameter is
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 * zero, it performs more or less like memmove. No copy is performed if
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 * source and destination addresses are equal. However the caches
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 * are synchronized. Note that the size is always rounded up to the
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 * next mutiple of 4.
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 */
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extern void * codemove(void *, const void *, unsigned int, unsigned long);
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extern void initialize_exceptions();
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typedef struct {
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  unsigned      EXC_SRR0;
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  unsigned      EXC_SRR1;
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  unsigned      _EXC_number;
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  unsigned      GPR0;
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  unsigned      GPR1;
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  unsigned      GPR2;
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  unsigned      GPR3;
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  unsigned      GPR4;
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  unsigned      GPR5;
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  unsigned      GPR6;
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  unsigned      GPR7;
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  unsigned      GPR8;
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  unsigned      GPR9;
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  unsigned      GPR10;
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  unsigned      GPR11;
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  unsigned      GPR12;
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  unsigned      GPR13;
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  unsigned      GPR14;
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  unsigned      GPR15;
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  unsigned      GPR16;
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  unsigned      GPR17;
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  unsigned      GPR18;
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  unsigned      GPR19;
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  unsigned      GPR20;
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  unsigned      GPR21;
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  unsigned      GPR22;
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  unsigned      GPR23;
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  unsigned      GPR24;
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  unsigned      GPR25;
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  unsigned      GPR26;
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  unsigned      GPR27;
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  unsigned      GPR28;
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  unsigned      GPR29;
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  unsigned      GPR30;
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  unsigned      GPR31;
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  unsigned      EXC_CR;
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  unsigned      EXC_CTR;
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  unsigned      EXC_XER;
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  unsigned      EXC_LR;
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  unsigned      EXC_MSR;
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  unsigned      EXC_DAR;
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}BSP_Exception_frame;
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typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
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extern exception_handler_t globalExceptHdl;
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/*
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 * Compatibility with pc386
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 */
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typedef BSP_Exception_frame CPU_Exception_frame;
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typedef exception_handler_t cpuExcHandlerType;
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#endif /* ASM */
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#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */

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