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/* shm_driver.h
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*
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* This include file contains all the constants, structures,
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* and global variables for this RTEMS based shared memory
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* communications interface driver.
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*
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* Processor board dependencies are in other files.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: shm_driver.h,v 1.2 2001-09-27 12:01:13 chris Exp $
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*/
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#ifndef __SHM_h
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#define __SHM_h
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#include <clockdrv.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The information contained in the Node Status, Locked Queue, and
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* Envelope Control Blocks must be maintained in a NEUTRAL format.
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* Currently the neutral format may be selected as big or little
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* endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
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*
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* It is CRITICAL to note that the neutral format can ONLY be
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* changed by modifying this file and recompiling the ENTIRE
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* SHM driver including ALL target specific support files.
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*
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* The following table details the memory contents for the endian
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* field of the Node Status Control Block in the various
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* data format configurations (data is in hexadecimal):
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*
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* NEUTRAL NATIVE BYTE 0 BYTE 1 BYTE 2 BYTE 3
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* ======= ====== ====== ====== ====== ======
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* BIG BIG 00 00 00 01
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* BIG LITTLE 10 00 00 00
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* LITTLE BIG 01 00 00 00
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* LITTLE LITTLE 00 00 00 10
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*
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*
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* NOTE: XXX
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* PORTABILITY OF LOCKING INSTRUCTIONS
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* ===================================
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* The locking mechanism described below is not
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* general enough. Where the hardware supports
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* it we should use "atomic swap" instructions
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* so the values in the lock can be tailored to
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* support a CPU with only weak atomic memory
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* instructions. There are combinations of
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* CPUs with inflexible atomic memory instructions
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* which appear to be incompatible. For example,
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* the SPARClite instruction uses a byte which is
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* 0xFF when locked. The PA-RISC uses 1 to indicate
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* locked and 0 when unlocked. These CPUs appear to
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* have incompatible lock instructions. But
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* they could be used in a heterogenous system
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* with does not mix SPARCs and PA-RISCs. For
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* example, the i386 and SPARC or i386 and SPARC
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* could work together. The bottom line is that
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* not every CPU will work together using this
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* locking scheme. There are supposed to be
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* algorithms to do this without hardware assist
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* and one of these should be incorporated into
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* the shared memory driver.
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*
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* The most flexible scheme using the instructions
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* of the various CPUs for efficiency would be to use
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* "atomic swaps" wherever possible. Make the lock
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* and unlock configurable much like BIG vs LITTLE
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* endian use of shared memory is now. The values
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* of the lock could then reflect the "worst"
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* CPU in a system. This still results in mixes
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* of CPUs which are incompatible.
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*
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* The current locking mechanism is based upon the MC68020
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* "tas" instruction which is atomic. All ports to other CPUs
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* comply with the restrictive placement of lock bit by this
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* instruction. The lock bit is the most significant bit in a
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* big-endian rtems_unsigned32. On other processors, the lock is
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* typically implemented via an atomic swap or atomic modify
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* bits type instruction.
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*/
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#define NEUTRAL_BIG
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#ifdef NEUTRAL_BIG
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#define SHM_BIG 0x00000001
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#define SHM_LITTLE 0x10000000
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#endif
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#ifdef NEUTRAL_LITTLE
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#define SHM_BIG 0x01000000
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#define SHM_LITTLE 0x00000010
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#endif
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/*
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* The following are the values used to fill in the lock field. Some CPUs
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* are able to write only a single value into field. By making the
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* lock and unlock values configurable, CPUs which support "atomic swap"
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* instructions can generally be made to work in any heterogeneous
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* configuration. However, it is possible for two CPUs to be incompatible
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* in regards to the lock field values. This occurs when two CPUs
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* which write only a single value to the field are used in a system
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* but the two CPUs write different incompatible values.
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*
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* NOTE: The following is a first attempt at defining values which
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* have a chance at working together. The m68k should use
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* chk2 instead of tas to be less restrictive. Target endian
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* problems (like the Force CPU386 which has (broken) big endian
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* view of the VMEbus address space) are not addressed yet.
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*/
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#if defined(__i960__)
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#define SHM_LOCK_VALUE 0x00000080
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#define SHM_UNLOCK_VALUE 0
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#elif defined(__mc68000__)
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#define SHM_LOCK_VALUE 0x80000000
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#define SHM_UNLOCK_VALUE 0
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#define SHM_LOCK_VALUE 0x80000000
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#define SHM_UNLOCK_VALUE 0
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#elif defined(__i386__)
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#define SHM_LOCK_VALUE 0x80000000
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#define SHM_UNLOCK_VALUE 0
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#elif defined(__mips__)
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#define SHM_LOCK_VALUE 0x80000000
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#define SHM_UNLOCK_VALUE 0
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#elif defined(__hppa__)
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#define SHM_LOCK_VALUE 0
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#define SHM_UNLOCK_VALUE 1
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#elif defined(__PPC__)
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#define SHM_LOCK_VALUE 1
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#define SHM_UNLOCK_VALUE 0
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#elif defined(__unix__)
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#define SHM_LOCK_VALUE 0
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#define SHM_UNLOCK_VALUE 1
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#elif defined(no_cpu) /* for this values are irrelevant */
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#define SHM_LOCK_VALUE 1
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#define SHM_UNLOCK_VALUE 0
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#else
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#error "shm_driver.h - no SHM_LOCK_VALUE defined for this CPU architecture"
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#endif
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#define Shm_Convert( value ) \
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((Shm_Configuration->convert) ? \
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(*Shm_Configuration->convert)(value) : (value))
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/* constants */
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#define SHM_MASTER 1 /* master initialization node */
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#define SHM_FIRST_NODE 1
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/* size constants */
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#define KILOBYTE (1024)
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#define MEGABYTE (1024*1024)
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/* inter-node interrupt values */
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#define NO_INTERRUPT 0 /* used for polled nodes */
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#define BYTE 1
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#define WORD 2
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#define LONG 4
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/* operational mode constants -- used in SHM Configuration Table */
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#define POLLED_MODE 0
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#define INTR_MODE 1
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/* error codes */
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#define NO_ERROR 0
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#define SHM_NO_FREE_PKTS 0xf0000
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/* null pointers of different types */
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#define NULL_ENV_CB ((Shm_Envelope_control *) 0)
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#define NULL_CONVERT 0
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/*
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* size of stuff before preamble in envelope.
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* It must be a constant since we will use it to generate MAX_PACKET_SIZE
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*/
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#define SHM_ENVELOPE_PREFIX_OVERHEAD (4 * sizeof(vol_u32))
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/*
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* The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long.
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* It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h.
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*/
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#ifndef MAX_ENVELOPE_SIZE
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#define MAX_ENVELOPE_SIZE 0x180
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#endif
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#define MAX_PACKET_SIZE (MAX_ENVELOPE_SIZE - \
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SHM_ENVELOPE_PREFIX_OVERHEAD + \
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sizeof(Shm_Envelope_preamble) + \
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sizeof(Shm_Envelope_postamble))
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/* constants pertinent to Locked Queue routines */
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#define LQ_UNLOCKED SHM_UNLOCK_VALUE
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#define LQ_LOCKED SHM_LOCK_VALUE
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/* constants related to the Free Envelope Pool */
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#define FREE_ENV_POOL 0
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#define FREE_ENV_CB (&Shm_Locked_queues[ FREE_ENV_POOL ])
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/* The following are important when dealing with
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* the shared memory communications interface area.
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*
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* NOTE: The starting address and length of the shared memory
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* is defined in a system dependent file.
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*/
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#define START_NS_CBS ((void *)Shm_Configuration->base)
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#define START_LQ_CBS ((START_NS_CBS) + \
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( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
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#define START_ENVELOPES ( ((void *) START_LQ_CBS) + \
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( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
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#define END_SHMCI_AREA ( (void *) START_ENVELOPES + \
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( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
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#define END_SHARED_MEM (START_NS_CBS+Shm_Configuration->length)
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/* macros */
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#define Shm_Is_master_node() \
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( SHM_MASTER == Shm_Local_node )
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#define Shm_Free_envelope( ecb ) \
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Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
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#define Shm_Allocate_envelope() \
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Shm_Locked_queue_Get(FREE_ENV_CB)
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#define Shm_Initialize_receive_queue(node) \
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Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
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#define Shm_Append_to_receive_queue(node, ecb) \
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Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
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#define Shm_Envelope_control_to_packet_prefix_pointer(ecb) \
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((void *)(ecb)->packet)
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#define Shm_Packet_prefix_to_envelope_control_pointer( pkt ) \
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((Shm_Envelope_control *)((rtems_unsigned8 *)(pkt) - \
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(sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD)))
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#define Shm_Build_preamble(ecb, node) \
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(ecb)->Preamble.endian = Shm_Configuration->format
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#define Shm_Build_postamble( ecb )
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/* volatile types */
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typedef volatile rtems_unsigned8 vol_u8;
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typedef volatile rtems_unsigned32 vol_u32;
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/* shm control information */
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struct shm_info {
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vol_u32 not_currently_used_0;
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vol_u32 not_currently_used_1;
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vol_u32 not_currently_used_2;
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vol_u32 not_currently_used_3;
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};
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typedef struct {
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/*byte start_of_text;*/
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vol_u32 endian;
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vol_u32 not_currently_used_0;
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vol_u32 not_currently_used_1;
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vol_u32 not_currently_used_2;
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} Shm_Envelope_preamble;
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typedef struct {
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} Shm_Envelope_postamble;
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/* WARNING! If you change this structure, don't forget to change
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* SHM_ENVELOPE_PREFIX_OVERHEAD and
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* Shm_Packet_prefix_to_envelope_control_pointer() above.
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*/
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/* This comment block describes the contents of each field
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* of the Envelope Control Block:
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*
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* next - The index of the next envelope on this queue.
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* queue - The index of the queue this envelope is on.
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* index - The index of this envelope.
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* Preamble - Generic packet preamble. One day this structure
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* could be enhanced to contain routing information.
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* packet - RTEMS MPCI packet. Untouched by SHM Driver
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* other than copying and format conversion as
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* documented in the RTEMS User's Guide.
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* Postamble - Generic packet postamble. One day this structure
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* could be enhanced to contain checksum information.
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*/
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typedef struct {
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vol_u32 next; /* next envelope on queue */
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vol_u32 queue; /* queue on which this resides */
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vol_u32 index; /* index into array of envelopes*/
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vol_u32 pad0; /* insure the next one is aligned */
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Shm_Envelope_preamble Preamble; /* header information */
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vol_u8 packet[MAX_PACKET_SIZE]; /* RTEMS INFO */
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Shm_Envelope_postamble Postamble;/* trailer information */
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} Shm_Envelope_control;
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/* This comment block describes the contents of each field
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* of the Locked Queue Control Block:
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*
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* lock - Lock used to insure mutually exclusive access.
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* front - Index of first envelope on queue. This field
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* is used to remove head of queue (receive).
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* rear - Index of last envelope on queue. This field
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* is used to add evelope to queue (send).
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* owner - The node number of the recipient (owning) node.
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* RTEMS does not use the node number zero (0).
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* The zero node is used by the SHM Driver for the
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* Free Envelope Queue shared by all nodes.
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*/
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typedef struct {
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vol_u32 lock; /* lock field for this queue */
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vol_u32 front; /* first envelope on queue */
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vol_u32 rear; /* last envelope on queue */
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vol_u32 owner; /* receiving (i.e. owning) node */
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} Shm_Locked_queue_Control;
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/* This comment block describes the contents of each field
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* of the Node Status Control Block:
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*
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* status - Node status. Current values are Pending Initialization,
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* Initialization Complete, and Active Node. Other values
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* could be added to enhance fault tolerance.
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* error - Zero if the node has not failed. Otherwise,
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* this field contains a status indicating the
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* failure reason.
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|
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* int_address, int_value, and int_length
|
348 |
|
|
* - These field are the Interrupt Information table
|
349 |
|
|
* for this node in neutral format. This is how
|
350 |
|
|
* each node knows how to generate interrupts.
|
351 |
|
|
*/
|
352 |
|
|
|
353 |
|
|
typedef struct {
|
354 |
|
|
vol_u32 status; /* node status information */
|
355 |
|
|
vol_u32 error; /* fatal error code */
|
356 |
|
|
vol_u32 int_address; /* write here for interrupt */
|
357 |
|
|
vol_u32 int_value; /* this value causes interrupt */
|
358 |
|
|
vol_u32 int_length; /* for this length (0,1,2,4) */
|
359 |
|
|
vol_u32 not_currently_used_0;
|
360 |
|
|
vol_u32 not_currently_used_1;
|
361 |
|
|
vol_u32 not_currently_used_2;
|
362 |
|
|
} Shm_Node_status_control;
|
363 |
|
|
|
364 |
|
|
/* This comment block describes the contents of each field
|
365 |
|
|
* of the Interrupt Information Table. This table describes
|
366 |
|
|
* how another node can generate an interrupt to this node.
|
367 |
|
|
* This information is target board dependent. If the
|
368 |
|
|
* SHM Driver is in POLLED_MODE, then all fields should
|
369 |
|
|
* be initialized to NO_INTERRUPT.
|
370 |
|
|
*
|
371 |
|
|
* address - The address to which another node should
|
372 |
|
|
* write to cause an interrupt.
|
373 |
|
|
* value - The value which must be written
|
374 |
|
|
* length - The size of the value to write. Valid
|
375 |
|
|
* values are BYTE, WORD, and LONG.
|
376 |
|
|
*
|
377 |
|
|
* NOTE: The Node Status Control Block contains this
|
378 |
|
|
* information in neutral format and not in a
|
379 |
|
|
* structure to avoid potential alignment problems.
|
380 |
|
|
*/
|
381 |
|
|
|
382 |
|
|
typedef struct {
|
383 |
|
|
vol_u32 *address; /* write here for interrupt */
|
384 |
|
|
vol_u32 value; /* this value causes interrupt */
|
385 |
|
|
vol_u32 length; /* for this length (0,1,2,4) */
|
386 |
|
|
} Shm_Interrupt_information;
|
387 |
|
|
|
388 |
|
|
/* SHM Configuration Table
|
389 |
|
|
*
|
390 |
|
|
* This comment block describes the contents of each field
|
391 |
|
|
* of the SHM Configuration Table.
|
392 |
|
|
*
|
393 |
|
|
* base - The base address of the shared memory. This
|
394 |
|
|
* address may be specific to this node.
|
395 |
|
|
* length - The length of the shared memory in bytes.
|
396 |
|
|
* format - The natural format for rtems_unsigned32's in the
|
397 |
|
|
* shared memory. Valid values are currently
|
398 |
|
|
* only SHM_LITTLE and SHM_BIG.
|
399 |
|
|
* convert - The address of the routine which converts
|
400 |
|
|
* between neutral and local format.
|
401 |
|
|
* poll_intr - The operational mode of the driver. Some
|
402 |
|
|
* target boards may not provide hardware for
|
403 |
|
|
* an interprocessor interrupt. If POLLED_MODE
|
404 |
|
|
* is selected, the SHM driver will install a
|
405 |
|
|
* wrapper around the Clock_isr() to poll for
|
406 |
|
|
* incoming packets. Throughput is dependent
|
407 |
|
|
* on the time between clock interrupts.
|
408 |
|
|
* Valid values are POLLED_MODE and INTR_MODE.
|
409 |
|
|
* cause_intr - This is the address of the routine used to
|
410 |
|
|
* write to a particular address and cause an
|
411 |
|
|
* interrupt on another node. This routine
|
412 |
|
|
* may need to be target dependent if something
|
413 |
|
|
* other than a normal write from C does not work.
|
414 |
|
|
* Intr - This structure describes the operation required
|
415 |
|
|
* to cause an interrupt to this node. The actual
|
416 |
|
|
* contents of this structure are described above.
|
417 |
|
|
*/
|
418 |
|
|
|
419 |
|
|
struct shm_config_info {
|
420 |
|
|
vol_u32 *base; /* base address of SHM */
|
421 |
|
|
vol_u32 length; /* length (in bytes) of SHM */
|
422 |
|
|
vol_u32 format; /* SHM is big or little endian */
|
423 |
|
|
vol_u32 (*convert)();/* neutral conversion routine */
|
424 |
|
|
vol_u32 poll_intr;/* POLLED or INTR driven mode */
|
425 |
|
|
void (*cause_intr)( rtems_unsigned32 );
|
426 |
|
|
Shm_Interrupt_information Intr; /* cause intr information */
|
427 |
|
|
};
|
428 |
|
|
|
429 |
|
|
typedef struct shm_config_info shm_config_table;
|
430 |
|
|
|
431 |
|
|
/* global variables */
|
432 |
|
|
|
433 |
|
|
#ifdef _SHM_INIT
|
434 |
|
|
#define SHM_EXTERN
|
435 |
|
|
#else
|
436 |
|
|
#define SHM_EXTERN extern
|
437 |
|
|
#endif
|
438 |
|
|
|
439 |
|
|
SHM_EXTERN shm_config_table *Shm_Configuration;
|
440 |
|
|
SHM_EXTERN Shm_Interrupt_information *Shm_Interrupt_table;
|
441 |
|
|
SHM_EXTERN Shm_Node_status_control *Shm_Node_statuses;
|
442 |
|
|
SHM_EXTERN Shm_Locked_queue_Control *Shm_Locked_queues;
|
443 |
|
|
SHM_EXTERN Shm_Envelope_control *Shm_Envelopes;
|
444 |
|
|
SHM_EXTERN rtems_configuration_table *Shm_RTEMS_Configuration;
|
445 |
|
|
SHM_EXTERN rtems_multiprocessing_table *Shm_RTEMS_MP_Configuration;
|
446 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Receive_message_count;
|
447 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Null_message_count;
|
448 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Interrupt_count;
|
449 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Local_node;
|
450 |
|
|
SHM_EXTERN Shm_Locked_queue_Control *Shm_Local_receive_queue;
|
451 |
|
|
SHM_EXTERN Shm_Node_status_control *Shm_Local_node_status;
|
452 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_isrstat;
|
453 |
|
|
/* reported by shmdr */
|
454 |
|
|
|
455 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Pending_initialization;
|
456 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Initialization_complete;
|
457 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Active_node;
|
458 |
|
|
|
459 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Maximum_nodes;
|
460 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Maximum_envelopes;
|
461 |
|
|
|
462 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_End_of_list;
|
463 |
|
|
SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_Not_on_list;
|
464 |
|
|
|
465 |
|
|
/* functions */
|
466 |
|
|
|
467 |
|
|
/* locked queue routines */
|
468 |
|
|
void Shm_Locked_queue_Add(
|
469 |
|
|
Shm_Locked_queue_Control *, Shm_Envelope_control * );
|
470 |
|
|
Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
|
471 |
|
|
void Shm_Locked_queue_Initialize(
|
472 |
|
|
Shm_Locked_queue_Control *, rtems_unsigned32 );
|
473 |
|
|
/* Shm_Initialize_lock is CPU dependent */
|
474 |
|
|
/* Shm_Lock is CPU dependent */
|
475 |
|
|
/* Shm_Unlock is CPU dependent */
|
476 |
|
|
|
477 |
|
|
/* portable routines */
|
478 |
|
|
void Init_env_pool();
|
479 |
|
|
void Shm_Print_statistics( void );
|
480 |
|
|
void MPCI_Fatal( Internal_errors_Source, boolean, rtems_unsigned32 );
|
481 |
|
|
rtems_task Shm_Cause_interrupt( rtems_unsigned32 );
|
482 |
|
|
void Shm_Poll();
|
483 |
|
|
void Shm_setclockvec();
|
484 |
|
|
void Shm_Convert_packet( rtems_packet_prefix * );
|
485 |
|
|
|
486 |
|
|
/* CPU specific routines are inlined in shmcpu.h */
|
487 |
|
|
|
488 |
|
|
/* target specific routines */
|
489 |
|
|
void *Shm_Convert_address( void * );
|
490 |
|
|
void Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );
|
491 |
|
|
void Shm_isr();
|
492 |
|
|
void Shm_setvec( void );
|
493 |
|
|
|
494 |
|
|
void Shm_Initialize_lock( Shm_Locked_queue_Control * );
|
495 |
|
|
void Shm_Lock( Shm_Locked_queue_Control * );
|
496 |
|
|
void Shm_Unlock( Shm_Locked_queue_Control * );
|
497 |
|
|
|
498 |
|
|
/* MPCI entry points */
|
499 |
|
|
rtems_mpci_entry Shm_Get_packet(
|
500 |
|
|
rtems_packet_prefix **
|
501 |
|
|
);
|
502 |
|
|
|
503 |
|
|
rtems_mpci_entry Shm_Initialization( void );
|
504 |
|
|
|
505 |
|
|
rtems_mpci_entry Shm_Receive_packet(
|
506 |
|
|
rtems_packet_prefix **
|
507 |
|
|
);
|
508 |
|
|
|
509 |
|
|
rtems_mpci_entry Shm_Return_packet(
|
510 |
|
|
rtems_packet_prefix *
|
511 |
|
|
);
|
512 |
|
|
|
513 |
|
|
rtems_mpci_entry Shm_Send_packet(
|
514 |
|
|
rtems_unsigned32,
|
515 |
|
|
rtems_packet_prefix *
|
516 |
|
|
);
|
517 |
|
|
|
518 |
|
|
extern rtems_mpci_table MPCI_table;
|
519 |
|
|
|
520 |
|
|
#ifdef _SHM_INIT
|
521 |
|
|
|
522 |
|
|
/* multiprocessor communications interface (MPCI) table */
|
523 |
|
|
|
524 |
|
|
rtems_mpci_table MPCI_table = {
|
525 |
|
|
100000, /* default timeout value in ticks */
|
526 |
|
|
MAX_PACKET_SIZE, /* maximum packet size */
|
527 |
|
|
Shm_Initialization, /* initialization procedure */
|
528 |
|
|
Shm_Get_packet, /* get packet procedure */
|
529 |
|
|
Shm_Return_packet, /* return packet procedure */
|
530 |
|
|
Shm_Send_packet, /* packet send procedure */
|
531 |
|
|
Shm_Receive_packet /* packet receive procedure */
|
532 |
|
|
};
|
533 |
|
|
|
534 |
|
|
#endif
|
535 |
|
|
|
536 |
|
|
#ifdef __cplusplus
|
537 |
|
|
}
|
538 |
|
|
#endif
|
539 |
|
|
|
540 |
|
|
#endif
|
541 |
|
|
/* end of include file */
|