URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [sparc/] [erc32/] [include/] [bsp.h] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log


/*  bsp.h
 *
 *  This include file contains all SPARC simulator definitions.
 *
 *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
 *  Research Corporation (OAR) under contract to the European Space
 *  Agency (ESA).
 *
 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
 *  European Space Agency.
 *
 *  $Id: bsp.h,v 1.2 2001-09-27 12:01:13 chris Exp $
 */
 
#ifndef __SIS_h
#define __SIS_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <rtems.h>
#include <iosupp.h>
#include <erc32.h>
#include <clockdrv.h>
 
#include <console.h>
 
/*
 *  confdefs.h overrides for this BSP:
 *   - two termios serial ports
 *   - Interrupt stack space is not minimum if defined.
 */
 
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
 
/*
 *  Define the time limits for RTEMS Test Suite test durations.
 *  Long test and short test duration limits are provided.  These
 *  values are in seconds and need to be converted to ticks for the
 *  application.
 *
 */
 
#define MAX_LONG_TEST_DURATION       3   /* 3 seconds */
#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
 
/*
 *  Define the interrupt mechanism for Time Test 27
 *
 *  NOTE: Since the interrupt code for the SPARC supports both synchronous
 *        and asynchronous trap handlers, support for testing with both
 *        is included.
 */
 
#define SIS_USE_SYNCHRONOUS_TRAP  0
 
/*
 *  The synchronous trap is an arbitrarily chosen software trap.
 */
 
#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
 
#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
 
#define MUST_WAIT_FOR_INTERRUPT 1
 
#define Install_tm27_vector( handler ) \
  set_vector( (handler), TEST_VECTOR, 1 );
 
#define Cause_tm27_intr() \
  asm volatile( "ta 0x10; nop " );
 
#define Clear_tm27_intr()  
 
#define Lower_tm27_intr() 
 
/*
 *  The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
 */
 
#else   /* use a regular asynchronous trap */
 
#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
 
#define MUST_WAIT_FOR_INTERRUPT 1
 
#define Install_tm27_vector( handler ) \
  set_vector( (handler), TEST_VECTOR, 1 );
 
#define Cause_tm27_intr() \
  do { \
    ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE ); \
    nop(); \
    nop(); \
    nop(); \
  } while (0)
 
#define Clear_tm27_intr() \
  ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
 
#define Lower_tm27_intr()
 
#endif
 
/*
 *  Simple spin delay in microsecond units for device drivers.
 *  This is very dependent on the clock speed of the target.
 */
 
extern void Clock_delay(rtems_unsigned32 microseconds);
 
#define delay( microseconds ) Clock_delay(microseconds)
 
/* Constants */
 
/*
 *  Information placed in the linkcmds file.
 */
 
extern int   RAM_START;
extern int   RAM_END;
extern int   RAM_SIZE;
 
extern int   PROM_START;
extern int   PROM_END;
extern int   PROM_SIZE;
 
extern int   CLOCK_SPEED;
 
extern int   end;        /* last address in the program */
 
/*
 *  Device Driver Table Entries
 */
 
/*
 * NOTE: Use the standard Console driver entry
 */
 
/*
 * NOTE: Use the standard Clock driver entry
 */
 
 
/* miscellaneous stuff assumed to exist */
 
void bsp_cleanup( void );
 
void bsp_start( void );
 
rtems_isr_entry set_vector(                     /* returns old vector */
    rtems_isr_entry     handler,                /* isr routine        */
    rtems_vector_number vector,                 /* vector number      */
    int                 type                    /* RTEMS or RAW intr  */
);
 
void DEBUG_puts( char *string );
 
void BSP_fatal_return( void );
 
void bsp_spurious_initialize( void );
 
extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
 
extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
 
#ifdef __cplusplus
}
#endif
 
#endif
/* end of include file */

Line No.	Rev	Author	Line
1	30	unneback	`/* bsp.h`
2			`*`
3			`* This include file contains all SPARC simulator definitions.`
4			`*`
5			`* COPYRIGHT (c) 1989-1999.`
6			`* On-Line Applications Research Corporation (OAR).`
7			`*`
8			`* The license and distribution terms for this file may be`
9			`* found in the file LICENSE in this distribution or at`
10			`* http://www.OARcorp.com/rtems/license.html.`
11			`*`
12			`* Ported to ERC32 implementation of the SPARC by On-Line Applications`
13			`* Research Corporation (OAR) under contract to the European Space`
14			`* Agency (ESA).`
15			`*`
16			`* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.`
17			`* European Space Agency.`
18			`*`
19			`* $Id: bsp.h,v 1.2 2001-09-27 12:01:13 chris Exp $`
20			`*/`
21
22			`#ifndef __SIS_h`
23			`#define __SIS_h`
24
25			`#ifdef __cplusplus`
26			`extern "C" {`
27			`#endif`
28
29			`#include <rtems.h>`
30			`#include <iosupp.h>`
31			`#include <erc32.h>`
32			`#include <clockdrv.h>`
33
34			`#include <console.h>`
35
36			`/*`
37			`* confdefs.h overrides for this BSP:`
38			`* - two termios serial ports`
39			`* - Interrupt stack space is not minimum if defined.`
40			`*/`
41
42			`#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2`
43			`#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024)`
44
45			`/*`
46			`* Define the time limits for RTEMS Test Suite test durations.`
47			`* Long test and short test duration limits are provided. These`
48			`* values are in seconds and need to be converted to ticks for the`
49			`* application.`
50			`*`
51			`*/`
52
53			`#define MAX_LONG_TEST_DURATION 3 /* 3 seconds */`
54			`#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */`
55
56			`/*`
57			`* Define the interrupt mechanism for Time Test 27`
58			`*`
59			`* NOTE: Since the interrupt code for the SPARC supports both synchronous`
60			`* and asynchronous trap handlers, support for testing with both`
61			`* is included.`
62			`*/`
63
64			`#define SIS_USE_SYNCHRONOUS_TRAP 0`
65
66			`/*`
67			`* The synchronous trap is an arbitrarily chosen software trap.`
68			`*/`
69
70			`#if (SIS_USE_SYNCHRONOUS_TRAP == 1)`
71
72			`#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )`
73
74			`#define MUST_WAIT_FOR_INTERRUPT 1`
75
76			`#define Install_tm27_vector( handler ) \`
77			`set_vector( (handler), TEST_VECTOR, 1 );`
78
79			`#define Cause_tm27_intr() \`
80			`asm volatile( "ta 0x10; nop " );`
81
82			`#define Clear_tm27_intr()`
83
84			`#define Lower_tm27_intr()`
85
86			`/*`
87			`* The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.`
88			`*/`
89
90			`#else /* use a regular asynchronous trap */`
91
92			`#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1`
93			`#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )`
94
95			`#define MUST_WAIT_FOR_INTERRUPT 1`
96
97			`#define Install_tm27_vector( handler ) \`
98			`set_vector( (handler), TEST_VECTOR, 1 );`
99
100			`#define Cause_tm27_intr() \`
101			`do { \`
102			`ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE ); \`
103			`nop(); \`
104			`nop(); \`
105			`nop(); \`
106			`} while (0)`
107
108			`#define Clear_tm27_intr() \`
109			`ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )`
110
111			`#define Lower_tm27_intr()`
112
113			`#endif`
114
115			`/*`
116			`* Simple spin delay in microsecond units for device drivers.`
117			`* This is very dependent on the clock speed of the target.`
118			`*/`
119
120			`extern void Clock_delay(rtems_unsigned32 microseconds);`
121
122			`#define delay( microseconds ) Clock_delay(microseconds)`
123
124			`/* Constants */`
125
126			`/*`
127			`* Information placed in the linkcmds file.`
128			`*/`
129
130			`extern int RAM_START;`
131			`extern int RAM_END;`
132			`extern int RAM_SIZE;`
133
134			`extern int PROM_START;`
135			`extern int PROM_END;`
136			`extern int PROM_SIZE;`
137
138			`extern int CLOCK_SPEED;`
139
140			`extern int end; /* last address in the program */`
141
142			`/*`
143			`* Device Driver Table Entries`
144			`*/`
145
146			`/*`
147			`* NOTE: Use the standard Console driver entry`
148			`*/`
149
150			`/*`
151			`* NOTE: Use the standard Clock driver entry`
152			`*/`
153
154
155			`/* miscellaneous stuff assumed to exist */`
156
157			`void bsp_cleanup( void );`
158
159			`void bsp_start( void );`
160
161			`rtems_isr_entry set_vector( /* returns old vector */`
162			`rtems_isr_entry handler, /* isr routine */`
163			`rtems_vector_number vector, /* vector number */`
164			`int type /* RTEMS or RAW intr */`
165			`);`
166
167			`void DEBUG_puts( char *string );`
168
169			`void BSP_fatal_return( void );`
170
171			`void bsp_spurious_initialize( void );`
172
173			`extern rtems_configuration_table BSP_Configuration; /* owned by BSP */`
174
175			`extern rtems_cpu_table Cpu_table; /* owned by BSP */`
176
177			`#ifdef __cplusplus`
178			`}`
179			`#endif`
180
181			`#endif`
182			`/* end of include file */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libbsp/] [sparc/] [erc32/] [include/] [bsp.h] - Blame information for rev 30