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/* cpuModel.S
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*
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* This file contains all assembly code for the Intel Cpu identification.
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* It is based on linux cpu detection code.
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*
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* Intel also provides public similar code in the book
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* called :
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*
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* Pentium Processor Family
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* Developer Family
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* Volume 3 : Architecture and Programming Manual
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*
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* At the following place :
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*
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* Chapter 5 : Feature determination
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* Chapter 25: CPUID instruction
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*
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* COPYRIGHT (c) 1998 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: cpuModel.S,v 1.2 2001-09-27 12:01:22 chris Exp $
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*/
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#include
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#include
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BEGIN_CODE
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PUBLIC(checkCPUtypeSetCr0);
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/*
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* check Processor type: 386, 486, 6x86(L) or CPUID capable processor
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*/
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SYM (checkCPUtypeSetCr0):
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/*
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* Assume 386 for now
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*/
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movl $3, SYM (x86)
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/*
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* Start using the EFLAGS AC bit determination method described in
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* the book mentioned above page 5.1. If this bit can be set we
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* have a 486 or above.
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*/
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pushfl /* save EFLAGS */
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pushfl /* Get EFLAGS in EAX */
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popl eax
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movl eax,ecx /* save original EFLAGS in ECX */
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xorl $EFLAGS_ALIGN_CHECK,eax /* flip AC bit in EAX */
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pushl eax /* set EAX as EFLAGS */
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popfl
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pushfl /* Get new EFLAGS in EAX */
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popl eax
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xorl ecx,eax /* check if AC bit changed */
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andl $EFLAGS_ALIGN_CHECK,eax
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je is386 /* If not : we have a 386 */
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/*
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* Assume 486 for now
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*/
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movl $4,SYM (x86)
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movl ecx,eax /* Restore orig EFLAGS in EAX */
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xorl $EFLAGS_ID,eax /* flip ID flag */
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pushl eax /* set EAX as EFLAGS */
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popfl
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pushfl /* Get new EFLAGS in EAX */
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popl eax
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xorl ecx,eax /* check if ID bit changed */
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andl $EFLAGS_ID,eax
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/*
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* if we are on a straight 486DX,
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* SX, or 487SX we can't change it
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* OTOH 6x86MXs and MIIs check OK
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* Also if we are on a Cyrix 6x86(L)
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*/
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je is486x
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isnew:
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/*
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* restore original EFLAGS
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*/
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popfl
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incl SYM(have_cpuid) /* we have CPUID instruction */
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/* use it to get :
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* processor type,
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* processor model,
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* processor mask,
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* by using it with EAX = 1
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*/
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movl $1, eax
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cpuid
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movb al, cl /* save reg for future use */
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andb $0x0f,ah /* mask processor family */
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movb ah,SYM (x86) /* put result in x86 var */
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andb $0xf0, al /* get model */
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shrb $4, al
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movb al,SYM (x86_model) /* store it in x86_model */
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andb $0x0f, cl /* get mask revision */
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movb cl,SYM (x86_mask) /* store it in x86_mask */
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movl edx,SYM(x86_capability) /* store feature flags in x86_capability */
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/* get vendor info by using CPUID with EXA = 0 */
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xorl eax, eax
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cpuid
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/*
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* store results contained in ebx, edx, ecx in
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* x86_vendor_id variable.
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*/
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movl ebx,SYM(x86_vendor_id)
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movl edx,SYM(x86_vendor_id)+4
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movl ecx,SYM(x86_vendor_id)+8
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movl cr0,eax /* 486+ */
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andl $(CR0_PAGING | CR0_PROTECTION_ENABLE | CR0_EXTENSION_TYPE), eax
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orl $(CR0_ALIGMENT_MASK | CR0_WRITE_PROTECT | CR0_NUMERIC_ERROR | CR0_MONITOR_COPROC),eax
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jmp 2f
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/* Now we test if we have a Cyrix 6x86(L). We didn't test before to avoid
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* clobbering the new BX chipset used with the Pentium II, which has a register
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* at the same addresses as those used to access the Cyrix special configuration
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* registers (CCRs).
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*/
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/*
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* A Cyrix/IBM 6x86(L) preserves flags after dividing 5 by 2
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* (and it _must_ be 5 divided by 2) while other CPUs change
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* them in undefined ways. We need to know this since we may
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* need to enable the CPUID instruction at least.
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* We couldn't use this test before since the PPro and PII behave
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* like Cyrix chips in this respect.
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*/
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is486x: xor ax,ax
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sahf
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movb $5,al
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movb $2,bl
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div bl
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lahf
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cmpb $2,ah
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jne ncyrix
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/*
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* N.B. The pattern of accesses to 0x22 and 0x23 is *essential*
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* so do not try to "optimize" it! For the same reason we
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* do all this with interrupts off.
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*/
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#define setCx86(reg, val) \
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movb reg,al; \
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outb al,$0x22; \
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movb val,al; \
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outb al,$0x23
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#define getCx86(reg) \
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movb reg,al; \
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outb al,$0x22; \
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inb $0x23,al
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cli
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getCx86($0xc3) /* get CCR3 */
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movb al,cl /* Save old value */
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movb al,bl
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andb $0x0f,bl /* Enable access to all config registers */
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orb $0x10,bl /* by setting bit 4 */
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setCx86($0xc3,bl)
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getCx86($0xe8) /* now we can get CCR4 */
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orb $0x80,al /* and set bit 7 (CPUIDEN) */
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movb al,bl /* to enable CPUID execution */
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setCx86($0xe8,bl)
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getCx86($0xfe) /* DIR0 : let's check this is a 6x86(L) */
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andb $0xf0,al /* should be 3xh */
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cmpb $0x30,al
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jne n6x86
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getCx86($0xe9) /* CCR5 : we reset the SLOP bit */
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andb $0xfd,al /* so that udelay calculation */
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movb al,bl /* is correct on 6x86(L) CPUs */
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setCx86($0xe9,bl)
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setCx86($0xc3,cl) /* Restore old CCR3 */
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sti
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jmp isnew /* We enabled CPUID now */
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n6x86: setCx86($0xc3,cl) /* Restore old CCR3 */
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sti
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ncyrix: /* restore original EFLAGS */
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popfl
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movl cr0,eax /* 486 */
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andl $(CR0_PAGING | CR0_EXTENSION_TYPE | CR0_PROTECTION_ENABLE),eax /* Save PG,PE,ET */
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orl $(CR0_ALIGMENT_MASK | CR0_WRITE_PROTECT | CR0_NUMERIC_ERROR | CR0_MONITOR_COPROC),eax /* set AM, WP, NE and MP */
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jmp 2f
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is386: /* restore original EFLAGS */
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popfl
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movl cr0,eax /* 386 */
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andl $(CR0_PAGING | CR0_EXTENSION_TYPE | CR0_PROTECTION_ENABLE),eax /* Save PG,PE,ET */
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orl $CR0_MONITOR_COPROC,eax /* set MP */
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2: movl eax,cr0
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call check_x87
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ret
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/*
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* We depend on ET to be correct. This checks for 287/387.
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*/
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check_x87:
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movb $0,SYM(hard_math)
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clts
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fninit
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fstsw ax
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cmpb $0,al
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je 1f
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movl cr0,eax /* no coprocessor: have to set bits */
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xorl $4,eax /* set EM */
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movl eax,cr0
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ret
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.align 16
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1: movb $1,SYM(hard_math)
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.byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
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ret
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END_CODE
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BEGIN_DATA
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PUBLIC(x86)
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PUBLIC(have_cpuid)
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PUBLIC(x86_model)
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PUBLIC(x86_mask)
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PUBLIC(x86_capability)
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PUBLIC(x86_vendor_id)
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PUBLIC(hard_math)
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SYM(x86):
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.byte 0
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SYM(have_cpuid):
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.long 0
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SYM(x86_model):
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.byte 0
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SYM(x86_mask):
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.byte 0
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SYM(x86_capability):
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.long 0
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SYM(x86_vendor_id):
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.zero 13
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SYM(hard_math):
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.byte 0
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END_DATA
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