URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [i386/] [registers.h] - Blame information for rev 173

Details | Compare with Previous | View Log


/* registers.h
 *
 *  This file contains definition and constants related to Intel Cpu
 *
 *  COPYRIGHT (c) 1998 valette@crf.canon.fr
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: registers.h,v 1.2 2001-09-27 12:01:22 chris Exp $
 */
 
#ifndef _LIBCPU_i386_REGISTERS_H
#define _LIBCPU_i386_REGISTERS_H
 
/*
 * definition related to EFLAGS
 */
#define EFLAGS_CARRY                    0x1
#define EFLAGS_PARITY                   0x4
 
#define EFLAGS_AUX_CARRY                0x10
#define EFLAGS_ZERO                     0x40
#define EFLAGS_SIGN                     0x80
 
#define EFLAGS_TRAP                     0x100
#define EFLAGS_INTR_ENABLE              0x200
#define EFLAGS_DIRECTION                0x400
#define EFLAGS_OVERFLOW                 0x800
 
#define EFLAGS_IOPL_MASK                0x3000
#define EFLAGS_NESTED_TASK              0x8000
 
#define EFLAGS_RESUME                   0x10000
#define EFLAGS_VIRTUAL_MODE             0x20000
#define EFLAGS_ALIGN_CHECK              0x40000
#define EFLAGS_VIRTUAL_INTR             0x80000
 
#define EFLAGS_VIRTUAL_INTR_PEND        0x100000
#define EFLAGS_ID                       0x200000
 
/*
 * definitions related to CR0
 */
#define CR0_PROTECTION_ENABLE           0x1
#define CR0_MONITOR_COPROC              0x2
#define CR0_COPROC_SOFT_EMUL            0x4
#define CR0_FLOATING_INSTR_EXCEPTION    0x8
 
#define CR0_EXTENSION_TYPE              0x10
#define CR0_NUMERIC_ERROR               0x20
 
#define CR0_WRITE_PROTECT               0x10000
#define CR0_ALIGMENT_MASK               0x40000
 
#define CR0_NO_WRITE_THROUGH            0x20000000
#define CR0_PAGE_LEVEL_CACHE_DISABLE    0x40000000
#define CR0_PAGING                      0x80000000
 
/*
 * definitions related to CR3
 */
 
#define CR3_PAGE_CACHE_DISABLE          0x10
#define CR3_PAGE_WRITE_THROUGH          0x8
 
 
#ifndef ASM
 
/*
 * definition of eflags registers has a bit field structure
 */
typedef struct {
  /*
   * fist byte : bits 0->7
   */
  unsigned int carry                    : 1;
  unsigned int                          : 1;
  unsigned int parity                   : 1;
  unsigned int                          : 1;
 
  unsigned int auxiliary_carry          : 1;
  unsigned int                          : 1;
  unsigned int zero                     : 1;    /* result is zero */
  unsigned int sign                     : 1;    /* result is less than zero */
  /*
   * Second byte : bits 7->15
   */
  unsigned int trap                     : 1;
  unsigned int intr_enable              : 1;    /* set => intr on */
  unsigned int direction                : 1;    /* set => autodecrement */
  unsigned int overflow                 : 1;
 
  unsigned int IO_privilege             : 2;
  unsigned int nested_task              : 1;
  unsigned int                          : 1;
  /*
   * Third byte : bits 15->23
   */
  unsigned int resume                   : 1;
  unsigned int virtual_mode             : 1;
  unsigned int aligment_check           : 1;
  unsigned int virtual_intr             : 1;
 
  unsigned int virtual_intr_pending     : 1;
  unsigned int id                       : 1;
  unsigned int                          : 2;
 
  /*
   * fourth byte : bits 24->31 : UNUSED
   */
  unsigned int                          : 8;
}eflags_bits;
 
typedef union {
  eflags_bits   eflags;
  unsigned int  i;
}eflags;
/*
 * definition of eflags registers has a bit field structure
 */
typedef struct {
  /*
   * fist byte : bits 0->7
   */
  unsigned int protection_enable        : 1;
  unsigned int monitor_coproc           : 1;
  unsigned int coproc_soft_emul         : 1;
  unsigned int floating_instr_except    : 1;
 
  unsigned int extension_type           : 1;
  unsigned int numeric_error            : 1;
  unsigned int                          : 2;
  /*
   * second byte 8->15 : UNUSED
   */
  unsigned int                          : 8;
  /*
   * third byte 16->23
   */
  unsigned int write_protect            : 1;
  unsigned int                          : 1;
  unsigned int aligment_mask            : 1;
  unsigned int                          : 1;
 
  unsigned int                          : 4;
  /*
   * fourth byte 24->31
   */
  unsigned int                          : 4;
 
  unsigned int                          : 1;
  unsigned int no_write_through         : 1;
  unsigned int page_level_cache_disable : 1;
  unsigned int paging   : 1;
}cr0_bits;
 
typedef union {
  cr0_bits      cr0;
  unsigned int  i;
}cr0;
 
/*
 * definition of cr3 registers has a bit field structure
 */
typedef struct {
 
  unsigned int                          : 3;
  unsigned int page_write_transparent   : 1;
  unsigned int page_cache_disable       : 1;
  unsigned int                          : 7;
  unsigned int page_directory_base      :20;
}cr3_bits;
 
typedef union {
  cr3_bits      cr3;
  unsigned int  i;
}cr3;
 
#endif
 
#endif
 

Line No.	Rev	Author	Line
1	30	unneback	`/* registers.h`
2			`*`
3			`* This file contains definition and constants related to Intel Cpu`
4			`*`
5			`* COPYRIGHT (c) 1998 valette@crf.canon.fr`
6			`*`
7			`* The license and distribution terms for this file may be`
8			`* found in the file LICENSE in this distribution or at`
9			`* http://www.OARcorp.com/rtems/license.html.`
10			`*`
11			`* $Id: registers.h,v 1.2 2001-09-27 12:01:22 chris Exp $`
12			`*/`
13
14			`#ifndef _LIBCPU_i386_REGISTERS_H`
15			`#define _LIBCPU_i386_REGISTERS_H`
16
17			`/*`
18			`* definition related to EFLAGS`
19			`*/`
20			`#define EFLAGS_CARRY 0x1`
21			`#define EFLAGS_PARITY 0x4`
22
23			`#define EFLAGS_AUX_CARRY 0x10`
24			`#define EFLAGS_ZERO 0x40`
25			`#define EFLAGS_SIGN 0x80`
26
27			`#define EFLAGS_TRAP 0x100`
28			`#define EFLAGS_INTR_ENABLE 0x200`
29			`#define EFLAGS_DIRECTION 0x400`
30			`#define EFLAGS_OVERFLOW 0x800`
31
32			`#define EFLAGS_IOPL_MASK 0x3000`
33			`#define EFLAGS_NESTED_TASK 0x8000`
34
35			`#define EFLAGS_RESUME 0x10000`
36			`#define EFLAGS_VIRTUAL_MODE 0x20000`
37			`#define EFLAGS_ALIGN_CHECK 0x40000`
38			`#define EFLAGS_VIRTUAL_INTR 0x80000`
39
40			`#define EFLAGS_VIRTUAL_INTR_PEND 0x100000`
41			`#define EFLAGS_ID 0x200000`
42
43			`/*`
44			`* definitions related to CR0`
45			`*/`
46			`#define CR0_PROTECTION_ENABLE 0x1`
47			`#define CR0_MONITOR_COPROC 0x2`
48			`#define CR0_COPROC_SOFT_EMUL 0x4`
49			`#define CR0_FLOATING_INSTR_EXCEPTION 0x8`
50
51			`#define CR0_EXTENSION_TYPE 0x10`
52			`#define CR0_NUMERIC_ERROR 0x20`
53
54			`#define CR0_WRITE_PROTECT 0x10000`
55			`#define CR0_ALIGMENT_MASK 0x40000`
56
57			`#define CR0_NO_WRITE_THROUGH 0x20000000`
58			`#define CR0_PAGE_LEVEL_CACHE_DISABLE 0x40000000`
59			`#define CR0_PAGING 0x80000000`
60
61			`/*`
62			`* definitions related to CR3`
63			`*/`
64
65			`#define CR3_PAGE_CACHE_DISABLE 0x10`
66			`#define CR3_PAGE_WRITE_THROUGH 0x8`
67
68
69			`#ifndef ASM`
70
71			`/*`
72			`* definition of eflags registers has a bit field structure`
73			`*/`
74			`typedef struct {`
75			`/*`
76			`* fist byte : bits 0->7`
77			`*/`
78			`unsigned int carry : 1;`
79			`unsigned int : 1;`
80			`unsigned int parity : 1;`
81			`unsigned int : 1;`
82
83			`unsigned int auxiliary_carry : 1;`
84			`unsigned int : 1;`
85			`unsigned int zero : 1; /* result is zero */`
86			`unsigned int sign : 1; /* result is less than zero */`
87			`/*`
88			`* Second byte : bits 7->15`
89			`*/`
90			`unsigned int trap : 1;`
91			`unsigned int intr_enable : 1; /* set => intr on */`
92			`unsigned int direction : 1; /* set => autodecrement */`
93			`unsigned int overflow : 1;`
94
95			`unsigned int IO_privilege : 2;`
96			`unsigned int nested_task : 1;`
97			`unsigned int : 1;`
98			`/*`
99			`* Third byte : bits 15->23`
100			`*/`
101			`unsigned int resume : 1;`
102			`unsigned int virtual_mode : 1;`
103			`unsigned int aligment_check : 1;`
104			`unsigned int virtual_intr : 1;`
105
106			`unsigned int virtual_intr_pending : 1;`
107			`unsigned int id : 1;`
108			`unsigned int : 2;`
109
110			`/*`
111			`* fourth byte : bits 24->31 : UNUSED`
112			`*/`
113			`unsigned int : 8;`
114			`}eflags_bits;`
115
116			`typedef union {`
117			`eflags_bits eflags;`
118			`unsigned int i;`
119			`}eflags;`
120			`/*`
121			`* definition of eflags registers has a bit field structure`
122			`*/`
123			`typedef struct {`
124			`/*`
125			`* fist byte : bits 0->7`
126			`*/`
127			`unsigned int protection_enable : 1;`
128			`unsigned int monitor_coproc : 1;`
129			`unsigned int coproc_soft_emul : 1;`
130			`unsigned int floating_instr_except : 1;`
131
132			`unsigned int extension_type : 1;`
133			`unsigned int numeric_error : 1;`
134			`unsigned int : 2;`
135			`/*`
136			`* second byte 8->15 : UNUSED`
137			`*/`
138			`unsigned int : 8;`
139			`/*`
140			`* third byte 16->23`
141			`*/`
142			`unsigned int write_protect : 1;`
143			`unsigned int : 1;`
144			`unsigned int aligment_mask : 1;`
145			`unsigned int : 1;`
146
147			`unsigned int : 4;`
148			`/*`
149			`* fourth byte 24->31`
150			`*/`
151			`unsigned int : 4;`
152
153			`unsigned int : 1;`
154			`unsigned int no_write_through : 1;`
155			`unsigned int page_level_cache_disable : 1;`
156			`unsigned int paging : 1;`
157			`}cr0_bits;`
158
159			`typedef union {`
160			`cr0_bits cr0;`
161			`unsigned int i;`
162			`}cr0;`
163
164			`/*`
165			`* definition of cr3 registers has a bit field structure`
166			`*/`
167			`typedef struct {`
168
169			`unsigned int : 3;`
170			`unsigned int page_write_transparent : 1;`
171			`unsigned int page_cache_disable : 1;`
172			`unsigned int : 7;`
173			`unsigned int page_directory_base :20;`
174			`}cr3_bits;`
175
176			`typedef union {`
177			`cr3_bits cr3;`
178			`unsigned int i;`
179			`}cr3;`
180
181			`#endif`
182
183			`#endif`
184

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [i386/] [registers.h] - Blame information for rev 173