OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [m68k/] [m68040/] [fpsp/] [sto_res.S] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback 
//
2 
//      $Id: sto_res.S,v 1.2 2001-09-27 12:01:22 chris Exp $
3 
//
4 
//      sto_res.sa 3.1 12/10/90
5 
//
6 
//      Takes the result and puts it in where the user expects it.
7 
//      Library functions return result in fp0. If fp0 is not the
8 
//      users destination register then fp0 is moved to the the
9 
//      correct floating-point destination register.  fp0 and fp1
10 
//      are then restored to the original contents.
11 
//
12 
//      Input:  result in fp0,fp1
13 
//
14 
//              d2 & a0 should be kept unmodified
15 
//
16 
//      Output: moves the result to the true destination reg or mem
17 
//
18 
//      Modifies: destination floating point register
19 
//
20 
 
21 
//              Copyright (C) Motorola, Inc. 1990
22 
//                      All Rights Reserved
23 
//
24 
//      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
25 
//      The copyright notice above does not evidence any
26 
//      actual or intended publication of such source code.
27 
 
28 
STO_RES:        //idnt  2,1 | Motorola 040 Floating Point Software Package
29 
 
30 
 
31 
        |section        8
32 
 
33 
#include "fpsp.defs"
34 
 
35 
        .global sto_cos
36 
sto_cos:
37 
        bfextu          CMDREG1B(%a6){#13:#3},%d0       //extract cos destination
38 
        cmpib           #3,%d0          //check for fp0/fp1 cases
39 
        bles            c_fp0123
40 
        fmovemx %fp1-%fp1,-(%a7)
41 
        moveql          #7,%d1
42 
        subl            %d0,%d1         //d1 = 7- (dest. reg. no.)
43 
        clrl            %d0
44 
        bsetl           %d1,%d0         //d0 is dynamic register mask
45 
        fmovemx (%a7)+,%d0
46 
        rts
47 
c_fp0123:
48 
        cmpib           #0,%d0
49 
        beqs            c_is_fp0
50 
        cmpib           #1,%d0
51 
        beqs            c_is_fp1
52 
        cmpib           #2,%d0
53 
        beqs            c_is_fp2
54 
c_is_fp3:
55 
        fmovemx %fp1-%fp1,USER_FP3(%a6)
56 
        rts
57 
c_is_fp2:
58 
        fmovemx %fp1-%fp1,USER_FP2(%a6)
59 
        rts
60 
c_is_fp1:
61 
        fmovemx %fp1-%fp1,USER_FP1(%a6)
62 
        rts
63 
c_is_fp0:
64 
        fmovemx %fp1-%fp1,USER_FP0(%a6)
65 
        rts
66 
 
67 
 
68 
        .global sto_res
69 
sto_res:
70 
        bfextu          CMDREG1B(%a6){#6:#3},%d0        //extract destination register
71 
        cmpib           #3,%d0          //check for fp0/fp1 cases
72 
        bles            fp0123
73 
        fmovemx %fp0-%fp0,-(%a7)
74 
        moveql          #7,%d1
75 
        subl            %d0,%d1         //d1 = 7- (dest. reg. no.)
76 
        clrl            %d0
77 
        bsetl           %d1,%d0         //d0 is dynamic register mask
78 
        fmovemx (%a7)+,%d0
79 
        rts
80 
fp0123:
81 
        cmpib           #0,%d0
82 
        beqs            is_fp0
83 
        cmpib           #1,%d0
84 
        beqs            is_fp1
85 
        cmpib           #2,%d0
86 
        beqs            is_fp2
87 
is_fp3:
88 
        fmovemx %fp0-%fp0,USER_FP3(%a6)
89 
        rts
90 
is_fp2:
91 
        fmovemx %fp0-%fp0,USER_FP2(%a6)
92 
        rts
93 
is_fp1:
94 
        fmovemx %fp0-%fp0,USER_FP1(%a6)
95 
        rts
96 
is_fp0:
97 
        fmovemx %fp0-%fp0,USER_FP0(%a6)
98 
        rts
99 
 
100 
        |end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.