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unneback |
//
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// $Id: x_operr.S,v 1.2 2001-09-27 12:01:22 chris Exp $
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//
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// x_operr.sa 3.5 7/1/91
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//
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// fpsp_operr --- FPSP handler for operand error exception
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//
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// See 68040 User's Manual pp. 9-44f
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//
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// Note 1: For trap disabled 040 does the following:
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// If the dest is a fp reg, then an extended precision non_signaling
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// NAN is stored in the dest reg. If the dest format is b, w, or l and
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// the source op is a NAN, then garbage is stored as the result (actually
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// the upper 32 bits of the mantissa are sent to the integer unit). If
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// the dest format is integer (b, w, l) and the operr is caused by
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// integer overflow, or the source op is inf, then the result stored is
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// garbage.
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// There are three cases in which operr is incorrectly signaled on the
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// 040. This occurs for move_out of format b, w, or l for the largest
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// negative integer (-2^7 for b, -2^15 for w, -2^31 for l).
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//
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// On opclass = 011 fmove.(b,w,l) that causes a conversion
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// overflow -> OPERR, the exponent in wbte (and fpte) is:
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// byte 56 - (62 - exp)
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// word 48 - (62 - exp)
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// long 32 - (62 - exp)
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//
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// where exp = (true exp) - 1
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//
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| 30 |
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// So, wbtemp and fptemp will contain the following on erroneously
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// signalled operr:
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// fpts = 1
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// fpte = $4000 (15 bit externally)
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// byte fptm = $ffffffff ffffff80
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// word fptm = $ffffffff ffff8000
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// long fptm = $ffffffff 80000000
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//
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// Note 2: For trap enabled 040 does the following:
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// If the inst is move_out, then same as Note 1.
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// If the inst is not move_out, the dest is not modified.
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// The exceptional operand is not defined for integer overflow
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// during a move_out.
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//
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// Copyright (C) Motorola, Inc. 1990
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// All Rights Reserved
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//
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// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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// The copyright notice above does not evidence any
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// actual or intended publication of such source code.
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X_OPERR: //idnt 2,1 | Motorola 040 Floating Point Software Package
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|section 8
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#include "fpsp.defs"
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|xref mem_write
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|xref real_operr
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|xref real_inex
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|xref get_fline
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|xref fpsp_done
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|xref reg_dest
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.global fpsp_operr
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fpsp_operr:
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//
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link %a6,#-LOCAL_SIZE
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fsave -(%a7)
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moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
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fmovemx %fp0-%fp3,USER_FP0(%a6)
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fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
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//
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// Check if this is an opclass 3 instruction.
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// If so, fall through, else branch to operr_end
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//
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btstb #TFLAG,T_BYTE(%a6)
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beqs operr_end
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//
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// If the destination size is B,W,or L, the operr must be
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// handled here.
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//
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movel CMDREG1B(%a6),%d0
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bfextu %d0{#3:#3},%d0 //0=long, 4=word, 6=byte
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cmpib #0,%d0 //determine size; check long
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beq operr_long
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cmpib #4,%d0 //check word
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beq operr_word
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cmpib #6,%d0 //check byte
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beq operr_byte
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//
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// The size is not B,W,or L, so the operr is handled by the
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// kernel handler. Set the operr bits and clean up, leaving
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// only the integer exception frame on the stack, and the
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// fpu in the original exceptional state.
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//
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operr_end:
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bsetb #operr_bit,FPSR_EXCEPT(%a6)
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bsetb #aiop_bit,FPSR_AEXCEPT(%a6)
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moveml USER_DA(%a6),%d0-%d1/%a0-%a1
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fmovemx USER_FP0(%a6),%fp0-%fp3
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fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
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frestore (%a7)+
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unlk %a6
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bral real_operr
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| 110 |
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operr_long:
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moveql #4,%d1 //write size to d1
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moveb STAG(%a6),%d0 //test stag for nan
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andib #0xe0,%d0 //clr all but tag
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cmpib #0x60,%d0 //check for nan
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| 116 |
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beq operr_nan
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cmpil #0x80000000,FPTEMP_LO(%a6) //test if ls lword is special
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| 118 |
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bnes chklerr //if not equal, check for incorrect operr
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| 119 |
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bsr check_upper //check if exp and ms mant are special
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| 120 |
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tstl %d0
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bnes chklerr //if d0 is true, check for incorrect operr
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| 122 |
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movel #0x80000000,%d0 //store special case result
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bsr operr_store
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bra not_enabled //clean and exit
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//
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| 126 |
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// CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
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//
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| 128 |
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chklerr:
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| 129 |
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movew FPTEMP_EX(%a6),%d0
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| 130 |
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andw #0x7FFF,%d0 //ignore sign bit
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| 131 |
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cmpw #0x3FFE,%d0 //this is the only possible exponent value
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bnes chklerr2
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fixlong:
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movel FPTEMP_LO(%a6),%d0
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bsr operr_store
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bra not_enabled
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chklerr2:
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| 138 |
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movew FPTEMP_EX(%a6),%d0
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| 139 |
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andw #0x7FFF,%d0 //ignore sign bit
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| 140 |
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cmpw #0x4000,%d0
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| 141 |
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bcc store_max //exponent out of range
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| 142 |
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| 143 |
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movel FPTEMP_LO(%a6),%d0
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andl #0x7FFF0000,%d0 //look for all 1's on bits 30-16
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cmpl #0x7FFF0000,%d0
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| 146 |
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beqs fixlong
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| 147 |
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| 148 |
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tstl FPTEMP_LO(%a6)
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| 149 |
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bpls chklepos
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cmpl #0xFFFFFFFF,FPTEMP_HI(%a6)
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beqs fixlong
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bra store_max
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chklepos:
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| 154 |
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tstl FPTEMP_HI(%a6)
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beqs fixlong
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bra store_max
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| 158 |
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operr_word:
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| 159 |
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moveql #2,%d1 //write size to d1
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| 160 |
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moveb STAG(%a6),%d0 //test stag for nan
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| 161 |
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andib #0xe0,%d0 //clr all but tag
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| 162 |
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cmpib #0x60,%d0 //check for nan
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| 163 |
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beq operr_nan
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cmpil #0xffff8000,FPTEMP_LO(%a6) //test if ls lword is special
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bnes chkwerr //if not equal, check for incorrect operr
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bsr check_upper //check if exp and ms mant are special
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tstl %d0
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bnes chkwerr //if d0 is true, check for incorrect operr
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| 169 |
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movel #0x80000000,%d0 //store special case result
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bsr operr_store
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| 171 |
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bra not_enabled //clean and exit
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//
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// CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
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//
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chkwerr:
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| 176 |
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movew FPTEMP_EX(%a6),%d0
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andw #0x7FFF,%d0 //ignore sign bit
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| 178 |
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cmpw #0x3FFE,%d0 //this is the only possible exponent value
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bnes store_max
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| 180 |
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movel FPTEMP_LO(%a6),%d0
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swap %d0
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| 182 |
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bsr operr_store
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| 183 |
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bra not_enabled
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| 184 |
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| 185 |
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operr_byte:
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| 186 |
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moveql #1,%d1 //write size to d1
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| 187 |
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moveb STAG(%a6),%d0 //test stag for nan
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| 188 |
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andib #0xe0,%d0 //clr all but tag
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| 189 |
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cmpib #0x60,%d0 //check for nan
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| 190 |
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beqs operr_nan
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| 191 |
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cmpil #0xffffff80,FPTEMP_LO(%a6) //test if ls lword is special
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| 192 |
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bnes chkberr //if not equal, check for incorrect operr
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| 193 |
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bsr check_upper //check if exp and ms mant are special
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| 194 |
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tstl %d0
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| 195 |
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bnes chkberr //if d0 is true, check for incorrect operr
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| 196 |
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movel #0x80000000,%d0 //store special case result
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| 197 |
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bsr operr_store
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| 198 |
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bra not_enabled //clean and exit
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| 199 |
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//
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| 200 |
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// CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
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| 201 |
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//
|
| 202 |
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chkberr:
|
| 203 |
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movew FPTEMP_EX(%a6),%d0
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| 204 |
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andw #0x7FFF,%d0 //ignore sign bit
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| 205 |
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cmpw #0x3FFE,%d0 //this is the only possible exponent value
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| 206 |
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bnes store_max
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| 207 |
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movel FPTEMP_LO(%a6),%d0
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| 208 |
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asll #8,%d0
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| 209 |
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swap %d0
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| 210 |
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bsr operr_store
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| 211 |
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bra not_enabled
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| 212 |
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|
| 213 |
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//
|
| 214 |
|
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// This operr condition is not of the special case. Set operr
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| 215 |
|
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// and aiop and write the portion of the nan to memory for the
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| 216 |
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// given size.
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| 217 |
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//
|
| 218 |
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operr_nan:
|
| 219 |
|
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orl #opaop_mask,USER_FPSR(%a6) //set operr & aiop
|
| 220 |
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| 221 |
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movel ETEMP_HI(%a6),%d0 //output will be from upper 32 bits
|
| 222 |
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bsr operr_store
|
| 223 |
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bra end_operr
|
| 224 |
|
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//
|
| 225 |
|
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// Store_max loads the max pos or negative for the size, sets
|
| 226 |
|
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// the operr and aiop bits, and clears inex and ainex, incorrectly
|
| 227 |
|
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// set by the 040.
|
| 228 |
|
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//
|
| 229 |
|
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store_max:
|
| 230 |
|
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orl #opaop_mask,USER_FPSR(%a6) //set operr & aiop
|
| 231 |
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bclrb #inex2_bit,FPSR_EXCEPT(%a6)
|
| 232 |
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bclrb #ainex_bit,FPSR_AEXCEPT(%a6)
|
| 233 |
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fmovel #0,%FPSR
|
| 234 |
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| 235 |
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tstw FPTEMP_EX(%a6) //check sign
|
| 236 |
|
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blts load_neg
|
| 237 |
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movel #0x7fffffff,%d0
|
| 238 |
|
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bsr operr_store
|
| 239 |
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bra end_operr
|
| 240 |
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load_neg:
|
| 241 |
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movel #0x80000000,%d0
|
| 242 |
|
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bsr operr_store
|
| 243 |
|
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bra end_operr
|
| 244 |
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|
|
| 245 |
|
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//
|
| 246 |
|
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// This routine stores the data in d0, for the given size in d1,
|
| 247 |
|
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// to memory or data register as required. A read of the fline
|
| 248 |
|
|
// is required to determine the destination.
|
| 249 |
|
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//
|
| 250 |
|
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operr_store:
|
| 251 |
|
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movel %d0,L_SCR1(%a6) //move write data to L_SCR1
|
| 252 |
|
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movel %d1,-(%a7) //save register size
|
| 253 |
|
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bsrl get_fline //fline returned in d0
|
| 254 |
|
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movel (%a7)+,%d1
|
| 255 |
|
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bftst %d0{#26:#3} //if mode is zero, dest is Dn
|
| 256 |
|
|
bnes dest_mem
|
| 257 |
|
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//
|
| 258 |
|
|
// Destination is Dn. Get register number from d0. Data is on
|
| 259 |
|
|
// the stack at (a7). D1 has size: 1=byte,2=word,4=long/single
|
| 260 |
|
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//
|
| 261 |
|
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andil #7,%d0 //isolate register number
|
| 262 |
|
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cmpil #4,%d1
|
| 263 |
|
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beqs op_long //the most frequent case
|
| 264 |
|
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cmpil #2,%d1
|
| 265 |
|
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bnes op_con
|
| 266 |
|
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orl #8,%d0
|
| 267 |
|
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bras op_con
|
| 268 |
|
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op_long:
|
| 269 |
|
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orl #0x10,%d0
|
| 270 |
|
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op_con:
|
| 271 |
|
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movel %d0,%d1 //format size:reg for reg_dest
|
| 272 |
|
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bral reg_dest //call to reg_dest returns to caller
|
| 273 |
|
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// ;of operr_store
|
| 274 |
|
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//
|
| 275 |
|
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// Destination is memory. Get from integer exception frame
|
| 276 |
|
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// and call mem_write.
|
| 277 |
|
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//
|
| 278 |
|
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dest_mem:
|
| 279 |
|
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leal L_SCR1(%a6),%a0 //put ptr to write data in a0
|
| 280 |
|
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movel EXC_EA(%a6),%a1 //put user destination address in a1
|
| 281 |
|
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movel %d1,%d0 //put size in d0
|
| 282 |
|
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bsrl mem_write
|
| 283 |
|
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rts
|
| 284 |
|
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//
|
| 285 |
|
|
// Check the exponent for $c000 and the upper 32 bits of the
|
| 286 |
|
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// mantissa for $ffffffff. If both are true, return d0 clr
|
| 287 |
|
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// and store the lower n bits of the least lword of FPTEMP
|
| 288 |
|
|
// to d0 for write out. If not, it is a real operr, and set d0.
|
| 289 |
|
|
//
|
| 290 |
|
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check_upper:
|
| 291 |
|
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cmpil #0xffffffff,FPTEMP_HI(%a6) //check if first byte is all 1's
|
| 292 |
|
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bnes true_operr //if not all 1's then was true operr
|
| 293 |
|
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cmpiw #0xc000,FPTEMP_EX(%a6) //check if incorrectly signalled
|
| 294 |
|
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beqs not_true_operr //branch if not true operr
|
| 295 |
|
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cmpiw #0xbfff,FPTEMP_EX(%a6) //check if incorrectly signalled
|
| 296 |
|
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beqs not_true_operr //branch if not true operr
|
| 297 |
|
|
true_operr:
|
| 298 |
|
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movel #1,%d0 //signal real operr
|
| 299 |
|
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rts
|
| 300 |
|
|
not_true_operr:
|
| 301 |
|
|
clrl %d0 //signal no real operr
|
| 302 |
|
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rts
|
| 303 |
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|
|
| 304 |
|
|
//
|
| 305 |
|
|
// End_operr tests for operr enabled. If not, it cleans up the stack
|
| 306 |
|
|
// and does an rte. If enabled, it cleans up the stack and branches
|
| 307 |
|
|
// to the kernel operr handler with only the integer exception
|
| 308 |
|
|
// frame on the stack and the fpu in the original exceptional state
|
| 309 |
|
|
// with correct data written to the destination.
|
| 310 |
|
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//
|
| 311 |
|
|
end_operr:
|
| 312 |
|
|
btstb #operr_bit,FPCR_ENABLE(%a6)
|
| 313 |
|
|
beqs not_enabled
|
| 314 |
|
|
enabled:
|
| 315 |
|
|
moveml USER_DA(%a6),%d0-%d1/%a0-%a1
|
| 316 |
|
|
fmovemx USER_FP0(%a6),%fp0-%fp3
|
| 317 |
|
|
fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
|
| 318 |
|
|
frestore (%a7)+
|
| 319 |
|
|
unlk %a6
|
| 320 |
|
|
bral real_operr
|
| 321 |
|
|
|
| 322 |
|
|
not_enabled:
|
| 323 |
|
|
//
|
| 324 |
|
|
// It is possible to have either inex2 or inex1 exceptions with the
|
| 325 |
|
|
// operr. If the inex enable bit is set in the FPCR, and either
|
| 326 |
|
|
// inex2 or inex1 occurred, we must clean up and branch to the
|
| 327 |
|
|
// real inex handler.
|
| 328 |
|
|
//
|
| 329 |
|
|
ck_inex:
|
| 330 |
|
|
moveb FPCR_ENABLE(%a6),%d0
|
| 331 |
|
|
andb FPSR_EXCEPT(%a6),%d0
|
| 332 |
|
|
andib #0x3,%d0
|
| 333 |
|
|
beq operr_exit
|
| 334 |
|
|
//
|
| 335 |
|
|
// Inexact enabled and reported, and we must take an inexact exception.
|
| 336 |
|
|
//
|
| 337 |
|
|
take_inex:
|
| 338 |
|
|
moveb #INEX_VEC,EXC_VEC+1(%a6)
|
| 339 |
|
|
movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
|
| 340 |
|
|
orl #sx_mask,E_BYTE(%a6)
|
| 341 |
|
|
moveml USER_DA(%a6),%d0-%d1/%a0-%a1
|
| 342 |
|
|
fmovemx USER_FP0(%a6),%fp0-%fp3
|
| 343 |
|
|
fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
|
| 344 |
|
|
frestore (%a7)+
|
| 345 |
|
|
unlk %a6
|
| 346 |
|
|
bral real_inex
|
| 347 |
|
|
//
|
| 348 |
|
|
// Since operr is only an E1 exception, there is no need to frestore
|
| 349 |
|
|
// any state back to the fpu.
|
| 350 |
|
|
//
|
| 351 |
|
|
operr_exit:
|
| 352 |
|
|
moveml USER_DA(%a6),%d0-%d1/%a0-%a1
|
| 353 |
|
|
fmovemx USER_FP0(%a6),%fp0-%fp3
|
| 354 |
|
|
fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
|
| 355 |
|
|
unlk %a6
|
| 356 |
|
|
bral fpsp_done
|
| 357 |
|
|
|
| 358 |
|
|
|end
|
