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//
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// $Id: x_ovfl.S,v 1.2 2001-09-27 12:01:22 chris Exp $
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//
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// x_ovfl.sa 3.5 7/1/91
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//
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// fpsp_ovfl --- FPSP handler for overflow exception
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//
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// Overflow occurs when a floating-point intermediate result is
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// too large to be represented in a floating-point data register,
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// or when storing to memory, the contents of a floating-point
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// data register are too large to be represented in the
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// destination format.
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//
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// Trap disabled results
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//
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// If the instruction is move_out, then garbage is stored in the
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// destination. If the instruction is not move_out, then the
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// destination is not affected. For 68881 compatibility, the
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// following values should be stored at the destination, based
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// on the current rounding mode:
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//
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// RN Infinity with the sign of the intermediate result.
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// RZ Largest magnitude number, with the sign of the
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// intermediate result.
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// RM For pos overflow, the largest pos number. For neg overflow,
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// -infinity
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// RP For pos overflow, +infinity. For neg overflow, the largest
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// neg number
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//
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// Trap enabled results
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// All trap disabled code applies. In addition the exceptional
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// operand needs to be made available to the users exception handler
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// with a bias of $6000 subtracted from the exponent.
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//
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//
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// Copyright (C) Motorola, Inc. 1990
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// All Rights Reserved
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//
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// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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// The copyright notice above does not evidence any
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// actual or intended publication of such source code.
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X_OVFL: //idnt 2,1 | Motorola 040 Floating Point Software Package
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|section 8
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#include "fpsp.defs"
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|xref ovf_r_x2
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|xref ovf_r_x3
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|xref store
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|xref real_ovfl
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|xref real_inex
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|xref fpsp_done
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|xref g_opcls
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|xref b1238_fix
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.global fpsp_ovfl
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fpsp_ovfl:
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link %a6,#-LOCAL_SIZE
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fsave -(%a7)
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moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
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fmovemx %fp0-%fp3,USER_FP0(%a6)
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fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
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//
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// The 040 doesn't set the AINEX bit in the FPSR, the following
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// line temporarily rectifies this error.
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//
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bsetb #ainex_bit,FPSR_AEXCEPT(%a6)
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//
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bsrl ovf_adj //denormalize, round & store interm op
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//
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// if overflow traps not enabled check for inexact exception
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//
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btstb #ovfl_bit,FPCR_ENABLE(%a6)
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beqs ck_inex
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//
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btstb #E3,E_BYTE(%a6)
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beqs no_e3_1
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bfextu CMDREG3B(%a6){#6:#3},%d0 //get dest reg no
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bclrb %d0,FPR_DIRTY_BITS(%a6) //clr dest dirty bit
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bsrl b1238_fix
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movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
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orl #sx_mask,E_BYTE(%a6)
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no_e3_1:
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moveml USER_DA(%a6),%d0-%d1/%a0-%a1
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fmovemx USER_FP0(%a6),%fp0-%fp3
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fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
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frestore (%a7)+
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unlk %a6
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bral real_ovfl
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//
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// It is possible to have either inex2 or inex1 exceptions with the
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// ovfl. If the inex enable bit is set in the FPCR, and either
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// inex2 or inex1 occurred, we must clean up and branch to the
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// real inex handler.
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//
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ck_inex:
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// move.b FPCR_ENABLE(%a6),%d0
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// and.b FPSR_EXCEPT(%a6),%d0
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// andi.b #$3,%d0
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btstb #inex2_bit,FPCR_ENABLE(%a6)
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beqs ovfl_exit
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//
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// Inexact enabled and reported, and we must take an inexact exception.
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//
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take_inex:
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btstb #E3,E_BYTE(%a6)
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beqs no_e3_2
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bfextu CMDREG3B(%a6){#6:#3},%d0 //get dest reg no
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bclrb %d0,FPR_DIRTY_BITS(%a6) //clr dest dirty bit
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bsrl b1238_fix
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movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
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orl #sx_mask,E_BYTE(%a6)
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no_e3_2:
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moveb #INEX_VEC,EXC_VEC+1(%a6)
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moveml USER_DA(%a6),%d0-%d1/%a0-%a1
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fmovemx USER_FP0(%a6),%fp0-%fp3
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fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
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frestore (%a7)+
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unlk %a6
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bral real_inex
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ovfl_exit:
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bclrb #E3,E_BYTE(%a6) //test and clear E3 bit
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beqs e1_set
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//
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// Clear dirty bit on dest resister in the frame before branching
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// to b1238_fix.
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//
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bfextu CMDREG3B(%a6){#6:#3},%d0 //get dest reg no
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bclrb %d0,FPR_DIRTY_BITS(%a6) //clr dest dirty bit
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bsrl b1238_fix //test for bug1238 case
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movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
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orl #sx_mask,E_BYTE(%a6)
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moveml USER_DA(%a6),%d0-%d1/%a0-%a1
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fmovemx USER_FP0(%a6),%fp0-%fp3
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fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
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frestore (%a7)+
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unlk %a6
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bral fpsp_done
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e1_set:
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moveml USER_DA(%a6),%d0-%d1/%a0-%a1
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fmovemx USER_FP0(%a6),%fp0-%fp3
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fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
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unlk %a6
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bral fpsp_done
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//
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// ovf_adj
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//
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ovf_adj:
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//
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// Have a0 point to the correct operand.
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//
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btstb #E3,E_BYTE(%a6) //test E3 bit
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beqs ovf_e1
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lea WBTEMP(%a6),%a0
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bras ovf_com
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ovf_e1:
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lea ETEMP(%a6),%a0
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ovf_com:
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bclrb #sign_bit,LOCAL_EX(%a0)
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sne LOCAL_SGN(%a0)
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bsrl g_opcls //returns opclass in d0
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cmpiw #3,%d0 //check for opclass3
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bnes not_opc011
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//
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// FPSR_CC is saved and restored because ovf_r_x3 affects it. The
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// CCs are defined to be 'not affected' for the opclass3 instruction.
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//
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moveb FPSR_CC(%a6),L_SCR1(%a6)
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bsrl ovf_r_x3 //returns a0 pointing to result
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moveb L_SCR1(%a6),FPSR_CC(%a6)
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bral store //stores to memory or register
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not_opc011:
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bsrl ovf_r_x2 //returns a0 pointing to result
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bral store //stores to memory or register
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|end
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