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/*
 *  asm_utils.s
 *
 *  $Id: asm_utils.S,v 1.2 2001-09-27 12:01:25 chris Exp $
 *
 *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
 *
 *  This file contains the low-level support for moving exception
 *  exception code to appropriate location.
 *
 */
 
#include 
#include 
#include 
#include "asm.h"
 
        .globl  codemove
codemove:
        .type   codemove,@function
/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
        cmplw   cr1,r3,r4
        addi    r0,r5,3
        srwi.   r0,r0,2
        beq     cr1,4f  /* In place copy is not necessary */
        beq     7f      /* Protect against 0 count */
        mtctr   r0
        bge     cr1,2f
 
        la      r8,-4(r4)
        la      r7,-4(r3)
1:      lwzu    r0,4(r8)
        stwu    r0,4(r7)
        bdnz    1b
        b       4f
 
2:      slwi    r0,r0,2
        add     r8,r4,r0
        add     r7,r3,r0
3:      lwzu    r0,-4(r8)
        stwu    r0,-4(r7)
        bdnz    3b
 
/* Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:      cmpwi   r6,0
        add     r5,r3,r5
        beq     7f      /* Always flush prefetch queue in any case */
        subi    r0,r6,1
        andc    r3,r3,r0
        mr      r4,r3
5:      cmplw   r4,r5
        dcbst   0,r4
        add     r4,r4,r6
        blt     5b
        sync            /* Wait for all dcbst to complete on bus */
        mr      r4,r3
6:      cmplw   r4,r5
        icbi    0,r4
        add     r4,r4,r6
        blt     6b
7:      sync            /* Wait for all icbi to complete on bus */
        isync
        blr

Line No.	Rev	Author	Line
1	30	unneback	`/*`
2			`* asm_utils.s`
3			`*`
4			`* $Id: asm_utils.S,v 1.2 2001-09-27 12:01:25 chris Exp $`
5			`*`
6			`* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)`
7			`*`
8			`* This file contains the low-level support for moving exception`
9			`* exception code to appropriate location.`
10			`*`
11			`*/`
12
13			`#include`
14			`#include`
15			`#include`
16			`#include "asm.h"`
17
18			`.globl codemove`
19			`codemove:`
20			`.type codemove,@function`
21			`/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */`
22			`cmplw cr1,r3,r4`
23			`addi r0,r5,3`
24			`srwi. r0,r0,2`
25			`beq cr1,4f /* In place copy is not necessary */`
26			`beq 7f /* Protect against 0 count */`
27			`mtctr r0`
28			`bge cr1,2f`
29
30			`la r8,-4(r4)`
31			`la r7,-4(r3)`
32			`1: lwzu r0,4(r8)`
33			`stwu r0,4(r7)`
34			`bdnz 1b`
35			`b 4f`
36
37			`2: slwi r0,r0,2`
38			`add r8,r4,r0`
39			`add r7,r3,r0`
40			`3: lwzu r0,-4(r8)`
41			`stwu r0,-4(r7)`
42			`bdnz 3b`
43
44			`/* Now flush the cache: note that we must start from a cache aligned`
45			`* address. Otherwise we might miss one cache line.`
46			`*/`
47			`4: cmpwi r6,0`
48			`add r5,r3,r5`
49			`beq 7f /* Always flush prefetch queue in any case */`
50			`subi r0,r6,1`
51			`andc r3,r3,r0`
52			`mr r4,r3`
53			`5: cmplw r4,r5`
54			`dcbst 0,r4`
55			`add r4,r4,r6`
56			`blt 5b`
57			`sync /* Wait for all dcbst to complete on bus */`
58			`mr r4,r3`
59			`6: cmplw r4,r5`
60			`icbi 0,r4`
61			`add r4,r4,r6`
62			`blt 6b`
63			`7: sync /* Wait for all icbi to complete on bus */`
64			`isync`
65			`blr`

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [powerpc/] [mpc6xx/] [exceptions/] [asm_utils.S] - Blame information for rev 607