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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [powerpc/] [mpc821/] [vectors/] [vectors.S] - Blame information for rev 173

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/*  vectors.s   1.1 - 95/12/04
2
 *
3
 *  This file contains the assembly code for the PowerPC MPC821
4
 *  interrupt veneers for RTEMS.
5
 *
6
 *  Author: Jay Monkman (jmonkman@frasca.com)
7
 *
8
 *  Copyright (C) 1998 by Frasca International, Inc.
9
 *
10
 *  Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s:
11
 *
12
 *  Author:     Andrew Bray 
13
 *
14
 *  COPYRIGHT (c) 1995 by i-cubed ltd.
15
 *
16
 *  To anyone who acknowledges that this file is provided "AS IS"
17
 *  without any express or implied warranty:
18
 *      permission to use, copy, modify, and distribute this file
19
 *      for any purpose is hereby granted without fee, provided that
20
 *      the above copyright notice and this notice appears in all
21
 *      copies, and that the name of i-cubed limited not be used in
22
 *      advertising or publicity pertaining to distribution of the
23
 *      software without specific, written prior permission.
24
 *      i-cubed limited makes no representations about the suitability
25
 *      of this software for any purpose.
26
 *
27
 */
28
 
29
/*
30
 *  The issue with this file is getting it loaded at the right place.
31
 *  The first vector MUST be at address 0x????0100.
32
 *  How this is achieved is dependant on the tool chain.
33
 *
34
 *  However the basic mechanism for ELF assemblers is to create a
35
 *  section called ".vectors", which will be loaded to an address
36
 *  between 0x????0000 and 0x????0100 (inclusive) via a link script.
37
 *
38
 *  The basic mechanism for XCOFF assemblers is to place it in the
39
 *  normal text section, and arrange for this file to be located
40
 *  at an appropriate position on the linker command line.
41
 *
42
 *  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
43
 *  offset from 0x????0000 to the first location in the file.  This
44
 *  will be either 0x0000 or 0xfff0.
45
 *
46
 *  $Id: vectors.S,v 1.2 2001-09-27 12:01:28 chris Exp $
47
 */
48
 
49
#include "asm.h"
50
#include 
51
 
52
#ifndef PPC_VECTOR_FILE_BASE
53
#error "PPC_VECTOR_FILE_BASE is not defined."
54
#endif
55
 
56
        /* Where this file will be loaded */
57
        .set    file_base, PPC_VECTOR_FILE_BASE
58
 
59
        /* Offset to store reg 0 */
60
 
61
        .set    IP_LINK, 0
62
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
63
        .set    IP_0, (IP_LINK + 56)
64
#else
65
        .set    IP_0, (IP_LINK + 8)
66
#endif
67
        .set    IP_2, (IP_0 + 4)
68
 
69
        .set    IP_3, (IP_2 + 4)
70
        .set    IP_4, (IP_3 + 4)
71
        .set    IP_5, (IP_4 + 4)
72
        .set    IP_6, (IP_5 + 4)
73
 
74
        .set    IP_7, (IP_6 + 4)
75
        .set    IP_8, (IP_7 + 4)
76
        .set    IP_9, (IP_8 + 4)
77
        .set    IP_10, (IP_9 + 4)
78
 
79
        .set    IP_11, (IP_10 + 4)
80
        .set    IP_12, (IP_11 + 4)
81
        .set    IP_13, (IP_12 + 4)
82
        .set    IP_28, (IP_13 + 4)
83
 
84
        .set    IP_29, (IP_28 + 4)
85
        .set    IP_30, (IP_29 + 4)
86
        .set    IP_31, (IP_30 + 4)
87
        .set    IP_CR, (IP_31 + 4)
88
 
89
        .set    IP_CTR, (IP_CR + 4)
90
        .set    IP_XER, (IP_CTR + 4)
91
        .set    IP_LR, (IP_XER + 4)
92
        .set    IP_PC, (IP_LR + 4)
93
 
94
        .set    IP_MSR, (IP_PC + 4)
95
 
96
        .set    IP_END, (IP_MSR + 16)
97
 
98
        /* Vector offsets                        */
99
        .set    begin_vector,     0x0000
100
        .set    reset_vector,     0x0100
101
        .set    mach_vector,      0x0200
102
        .set    dsi_vector,       0x0300
103
        .set    isi_vector,       0x0400
104
        .set    ext_vector,       0x0500
105
        .set    align_vector,     0x0600
106
        .set    prog_vector,      0x0700
107
        .set    float_vector,     0x0800
108
        .set    dec_vector,       0x0900
109
        .set    sys_vector,       0x0C00
110
        .set    trace_vector,     0x0d00
111
        .set    syscall_vector,   0x0c00
112
        .set    fpassist_vector,  0x0e00
113
        .set    software_vector,  0x1000
114
        .set    itlbm_vector,     0x1100
115
        .set    dtlbm_vector,     0x1200
116
        .set    itlbe_vector,     0x1300
117
        .set    dtlbe_vector,     0x1400
118
        .set    databkpt_vector,  0x1c00
119
        .set    insbkpt_vector,   0x1d00
120
        .set    perbkpt_vector,   0x1e00
121
        .set    dev_vector,       0x1f00
122
        .set    siu_vector,       0x2000
123
        .set    cpm_vector,       0x2400
124
 
125
/* Go to the right section */
126
#if PPC_ASM == PPC_ASM_ELF
127
        .section .vectors,"awx",@progbits
128
#elif PPC_ASM == PPC_ASM_XCOFF
129
        .csect  .text[PR]
130
#endif
131
 
132
        PUBLIC_VAR (__vectors)
133
SYM (__vectors):
134
 
135
/* Critical error handling */
136
        .org    reset_vector - file_base
137
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
138
#if (PPC_HAS_FPU)
139
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
140
#else
141
        stwu    r1, -(20*4 + IP_END)(r1)
142
#endif
143
#else
144
        stwu    r1, -(IP_END)(r1)
145
#endif
146
        stw     r0, IP_0(r1)
147
 
148
        li      r0, PPC_IRQ_SYSTEM_RESET
149
        b       PROC (_ISR_Handler)
150
 
151
/* Machine check exception */
152
        .org    mach_vector - file_base
153
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
154
#if (PPC_HAS_FPU)
155
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
156
#else
157
        stwu    r1, -(20*4 + IP_END)(r1)
158
#endif
159
#else
160
        stwu    r1, -(IP_END)(r1)
161
#endif
162
        stw     r0, IP_0(r1)
163
 
164
        li      r0, PPC_IRQ_MCHECK
165
        b       PROC (_ISR_Handler)
166
 
167
/* Protection exception */
168
        .org    dsi_vector - file_base
169
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
170
#if (PPC_HAS_FPU)
171
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
172
#else
173
        stwu    r1, -(20*4 + IP_END)(r1)
174
#endif
175
#else
176
        stwu    r1, -(IP_END)(r1)
177
#endif
178
        stw     r0, IP_0(r1)
179
 
180
        li      r0, PPC_IRQ_PROTECT
181
        b       PROC (_ISR_Handler)
182
 
183
/* Instruction Storage exception */
184
        .org    isi_vector - file_base
185
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
186
#if (PPC_HAS_FPU)
187
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
188
#else
189
        stwu    r1, -(20*4 + IP_END)(r1)
190
#endif
191
#else
192
        stwu    r1, -(IP_END)(r1)
193
#endif
194
        stw     r0, IP_0(r1)
195
 
196
        li      r0, PPC_IRQ_ISI
197
        b       PROC (_ISR_Handler)
198
 
199
/* External interrupt */
200
/* When an external interrupt occurs, we must find out what caused it */
201
/*  before calling the RTEMS handler. First we use SIVEC to decide    */
202
/*  what signalled the interrupt to the SIU.                          */
203
        .org    ext_vector - file_base
204
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
205
#if (PPC_HAS_FPU)
206
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
207
#else
208
        stwu    r1, -(20*4 + IP_END)(r1)
209
#endif
210
#else
211
        stwu    r1, -(IP_END)(r1)
212
#endif
213
        stw     r0, IP_0(r1)
214
        stw     r9, IP_9(r1)    /* r9 will be restored in the next level */
215
        stw     r10, IP_10(r1)
216
 
217
        lis     r9, m821@ha
218
        addi    r9, r9, m821@l
219
        lbz     r10, 0x1c(r9)           /* SIVEC */
220
        rlwinm  r10, r10, 4, 0, 27      /* each psuedo vector will have */
221
                                        /* room for 16 instructions */
222
        addis   r10, r10, siu_vectors@ha
223
        addi    r10, r10, siu_vectors@l
224
        mflr    r0
225
        mtlr    r10
226
        lwz     r10, IP_10(r1)
227
        blr
228
 
229
/* Align exception */
230
        .org    align_vector - file_base
231
        .extern align_h
232
        b       align_h
233
 
234
/* Program exception */
235
        .org    prog_vector - file_base
236
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
237
#if (PPC_HAS_FPU)
238
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
239
#else
240
        stwu    r1, -(20*4 + IP_END)(r1)
241
#endif
242
#else
243
        stwu    r1, -(IP_END)(r1)
244
#endif
245
        stw     r0, IP_0(r1)
246
 
247
        li      r0, PPC_IRQ_PROGRAM
248
        b       PROC (_ISR_Handler)
249
 
250
/* Float exception */
251
        .org    float_vector - file_base
252
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
253
#if (PPC_HAS_FPU)
254
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
255
#else
256
        stwu    r1, -(20*4 + IP_END)(r1)
257
#endif
258
#else
259
        stwu    r1, -(IP_END)(r1)
260
#endif
261
        stw     r0, IP_0(r1)
262
 
263
        li      r0, PPC_IRQ_NOFP
264
        b       PROC (_ISR_Handler)
265
 
266
/* Decrementer exception */
267
        .org    dec_vector - file_base
268
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
269
#if (PPC_HAS_FPU)
270
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
271
#else
272
        stwu    r1, -(20*4 + IP_END)(r1)
273
#endif
274
#else
275
        stwu    r1, -(IP_END)(r1)
276
#endif
277
        stw     r0, IP_0(r1)
278
 
279
        li      r0, PPC_IRQ_PROGRAM
280
        b       PROC (_ISR_Handler)
281
 
282
/* System call */
283
        .org    sys_vector - file_base
284
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
285
#if (PPC_HAS_FPU)
286
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
287
#else
288
        stwu    r1, -(20*4 + IP_END)(r1)
289
#endif
290
#else
291
        stwu    r1, -(IP_END)(r1)
292
#endif
293
        stw     r0, IP_0(r1)
294
 
295
        li      r0, PPC_IRQ_SCALL
296
        b       PROC (_ISR_Handler)
297
 
298
/* Trace interrupt */
299
        .org    trace_vector - file_base
300
#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
301
#if (PPC_HAS_FPU)
302
        stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
303
#else
304
        stwu    r1, -(20*4 + IP_END)(r1)
305
#endif
306
#else
307
        stwu    r1, -(IP_END)(r1)
308
#endif
309
        stw     r0, IP_0(r1)
310
 
311
        li      r0, PPC_IRQ_TRACE
312
        b       PROC (_ISR_Handler)
313
 
314
        .org    itlbm_vector - file_base
315
itlbm_vectors:
316
        mfspr   r2, 784      /* MI_CTR */
317
        mfspr   r3, 792      /* MD_CTR */
318
        mfspr   r4, 787      /* MI_EPN */
319
        mfspr   r5, 789      /* MI_TWC */
320
        mfspr   r6, 797      /* MD_TWC */
321
        mfspr   r7, 789      /* MI_TWC */
322
        mfspr   r8, 790      /* MI_RPN */
323
        mfspr   r9, 798      /* MD_RPN */
324
        mfspr   r10, 796      /* M_TWB */
325
        mfspr   r11, 793      /* M_CASID */
326
        mfspr   r12, 786      /* MI_AP */
327
        mfspr   r13, 794      /* MD_AP */
328
        mfspr   r14, 799      /* M_TW */
329
        mfspr   r15, 816      /* MI_CAM */
330
        mfspr   r16, 817      /* MI_RAM0 */
331
        mfspr   r17, 818      /* MI_RAM1 */
332
        mfspr   r18, 824      /* MD_CAM */
333
        mfspr   r19, 825      /* M_RAM0 */
334
        mfspr   r20, 826      /* M_RAM1 */
335
        .long   0
336
 
337
        .org    dtlbm_vector - file_base
338
dtlbm_vectors:
339
        mfspr   r1, 0x1a
340
        mfspr   r2, 784      /* MI_CTR */
341
        mfspr   r3, 792      /* MD_CTR */
342
        lis     r3, 0x400
343
        mtspr   792, r3
344
        mfspr   r4, 787      /* MI_EPN */
345
        mfspr   r5, 789      /* MI_TWC */
346
        mfspr   r6, 797      /* MD_TWC */
347
        mfspr   r7, 789      /* MI_TWC */
348
        mfspr   r8, 790      /* MI_RPN */
349
        mfspr   r9, 798      /* MD_RPN */
350
        mfspr   r10, 796      /* M_TWB */
351
        mfspr   r11, 793      /* M_CASID */
352
        mfspr   r12, 786      /* MI_AP */
353
        mfspr   r13, 794      /* MD_AP */
354
        mfspr   r14, 799      /* M_TW */
355
        mfspr   r15, 816      /* MI_CAM */
356
        mfspr   r16, 817      /* MI_RAM0 */
357
        mfspr   r17, 818      /* MI_RAM1 */
358
        mtspr   824, r18
359
        mfspr   r18, 824      /* MD_CAM */
360
        mfspr   r19, 825      /* M_RAM0 */
361
        mfspr   r20, 826      /* M_RAM1 */
362
        .long   0
363
 
364
        .org    itlbe_vector - file_base
365
itlbe_vectors:
366
        mfspr   r2, 784      /* MI_CTR */
367
        mfspr   r3, 792      /* MD_CTR */
368
        mfspr   r4, 787      /* MI_EPN */
369
        mfspr   r5, 789      /* MI_TWC */
370
        mfspr   r6, 797      /* MD_TWC */
371
        mfspr   r7, 789      /* MI_TWC */
372
        mfspr   r8, 790      /* MI_RPN */
373
        mfspr   r9, 798      /* MD_RPN */
374
        mfspr   r10, 796      /* M_TWB */
375
        mfspr   r11, 793      /* M_CASID */
376
        mfspr   r12, 786      /* MI_AP */
377
        mfspr   r13, 794      /* MD_AP */
378
        mfspr   r14, 799      /* M_TW */
379
        mfspr   r15, 816      /* MI_CAM */
380
        mfspr   r16, 817      /* MI_RAM0 */
381
        mfspr   r17, 818      /* MI_RAM1 */
382
        mfspr   r18, 824      /* MD_CAM */
383
        mfspr   r19, 825      /* M_RAM0 */
384
        mfspr   r20, 826      /* M_RAM1 */
385
        .long   0
386
 
387
        .org    dtlbe_vector - file_base
388
dtlbe_vectors:
389
        mfspr   r2, 784      /* MI_CTR */
390
        mfspr   r3, 792      /* MD_CTR */
391
        mfspr   r4, 787      /* MI_EPN */
392
        mfspr   r5, 789      /* MI_TWC */
393
        mfspr   r6, 797      /* MD_TWC */
394
        mfspr   r7, 789      /* MI_TWC */
395
        mfspr   r8, 790      /* MI_RPN */
396
        mfspr   r9, 798      /* MD_RPN */
397
        mfspr   r10, 796      /* M_TWB */
398
        mfspr   r11, 793      /* M_CASID */
399
        mfspr   r12, 786      /* MI_AP */
400
        mfspr   r13, 794      /* MD_AP */
401
        mfspr   r14, 799      /* M_TW */
402
        mfspr   r15, 816      /* MI_CAM */
403
        mfspr   r16, 817      /* MI_RAM0 */
404
        mfspr   r17, 818      /* MI_RAM1 */
405
        mfspr   r18, 824      /* MD_CAM */
406
        mfspr   r19, 825      /* M_RAM0 */
407
        mfspr   r20, 826      /* M_RAM1 */
408
        .long   0
409
 
410
 
411
 
412
/* Now we look at what signaled the interrupt to the SIU. */
413
/*   I needed to do this in order to decode the CPM interrupts before  */
414
/*    calling _ISR_Handler                                             */
415
 
416
/* *IRQ0 */
417
        .org    siu_vector - file_base
418
siu_vectors:
419
        mtlr    r0
420
        lwz     r9, IP_9(r1)
421
        li      r0, PPC_IRQ_IRQ0
422
        b       PROC (_ISR_Handler)
423
 
424
        nop
425
        nop
426
        nop
427
        nop
428
        nop
429
        nop
430
        nop
431
        nop
432
        nop
433
        nop
434
        nop
435
        nop
436
 
437
/* Level 0 */
438
        mtlr    r0
439
        lwz     r9, IP_9(r1)
440
        li      r0, PPC_IRQ_LVL0
441
        b       PROC (_ISR_Handler)
442
 
443
        nop
444
        nop
445
        nop
446
        nop
447
        nop
448
        nop
449
        nop
450
        nop
451
        nop
452
        nop
453
        nop
454
        nop
455
 
456
/* *IRQ1 */
457
        mtlr    r0
458
        lwz     r9, IP_9(r1)
459
        li      r0, PPC_IRQ_IRQ1
460
        b       PROC (_ISR_Handler)
461
 
462
        nop
463
        nop
464
        nop
465
        nop
466
        nop
467
        nop
468
        nop
469
        nop
470
        nop
471
        nop
472
        nop
473
        nop
474
 
475
/* This is probably not the "correct" way to do this. I need to have a
476
 *  way of calling _ISR_Handler for the CPM interrupts and this is the
477
 *  simplest way I can think of. Since I have the CPM interrupt mapped
478
 *  to the SIU interrupt level 1 on the eth-comm board, I put it here.
479
 *  It would probably be ok if I moved this directory to under libbsp
480
 *  instead of libcpu. For now, deal with it.
481
*/
482
/* Level 1 - CPM */
483
/* Now we need to get the CPM interrupt vector */
484
        /* Registers:                                 */
485
        /*   R0 - has stored value of LR              */
486
        /*   R9 - pointer to m821 struct              */
487
        /*   R10 has already been saved and restored  */
488
        li      r10, 1
489
        sth     r10, 0x930(r9)       /* CIVR */
490
        lbz     r10, 0x930(r9)       /* if we use this as an offset into a */
491
        rlwinm  r10, r10, 1, 0, 31   /*  table, each entry will have room  */
492
                                     /*  4 instructions.                   */
493
        addis   r10, r10, cpm_vectors@ha
494
        addi    r10, r10, cpm_vectors@l
495
 
496
        mtlr    r10
497
        lwz     r10, IP_10(r1)
498
        blr
499
 
500
        nop
501
        nop
502
        nop
503
        nop
504
        nop
505
        nop
506
        nop
507
 
508
#if 0
509
/* Level 1 */
510
        mtlr    r0
511
        lwz     r9, IP_9(r1)
512
        li      r0, PPC_IRQ_LVL1
513
        b       PROC (_ISR_Handler)
514
 
515
        nop
516
        nop
517
        nop
518
        nop
519
        nop
520
        nop
521
        nop
522
        nop
523
        nop
524
        nop
525
        nop
526
        nop
527
#endif
528
 
529
/* *IRQ2 */
530
        mtlr    r0
531
        lwz     r9, IP_9(r1)
532
        li      r0, PPC_IRQ_IRQ2
533
        b       PROC (_ISR_Handler)
534
 
535
        nop
536
        nop
537
        nop
538
        nop
539
        nop
540
        nop
541
        nop
542
        nop
543
        nop
544
        nop
545
        nop
546
        nop
547
 
548
/* Level 2 */
549
        mtlr    r0
550
        lwz     r9, IP_9(r1)
551
        li      r0, PPC_IRQ_LVL2
552
        b       PROC (_ISR_Handler)
553
 
554
        nop
555
        nop
556
        nop
557
        nop
558
        nop
559
        nop
560
        nop
561
        nop
562
        nop
563
        nop
564
        nop
565
        nop
566
 
567
/* *IRQ3 */
568
        mtlr    r0
569
        lwz     r9, IP_9(r1)
570
        li      r0, PPC_IRQ_IRQ3
571
        b       PROC (_ISR_Handler)
572
 
573
        nop
574
        nop
575
        nop
576
        nop
577
        nop
578
        nop
579
        nop
580
        nop
581
        nop
582
        nop
583
        nop
584
        nop
585
 
586
/* Level 3 */
587
        mtlr    r0
588
        lwz     r9, IP_9(r1)
589
        li      r0, PPC_IRQ_LVL3
590
        b       PROC (_ISR_Handler)
591
 
592
        nop
593
        nop
594
        nop
595
        nop
596
        nop
597
        nop
598
        nop
599
        nop
600
        nop
601
        nop
602
        nop
603
        nop
604
 
605
/* *IRQ4 */
606
        mtlr    r0
607
        lwz     r9, IP_9(r1)
608
        li      r0, PPC_IRQ_IRQ4
609
        b       PROC (_ISR_Handler)
610
 
611
        nop
612
        nop
613
        nop
614
        nop
615
        nop
616
        nop
617
        nop
618
        nop
619
        nop
620
        nop
621
        nop
622
        nop
623
 
624
/* Level 4 */
625
        mtlr    r0
626
        lwz     r9, IP_9(r1)
627
        li      r0, PPC_IRQ_LVL4
628
        b       PROC (_ISR_Handler)
629
 
630
        nop
631
        nop
632
        nop
633
        nop
634
        nop
635
        nop
636
        nop
637
        nop
638
        nop
639
        nop
640
        nop
641
        nop
642
 
643
/* *IRQ5 */
644
        mtlr    r0
645
        lwz     r9, IP_9(r1)
646
        li      r0, PPC_IRQ_IRQ5
647
        b       PROC (_ISR_Handler)
648
 
649
        nop
650
        nop
651
        nop
652
        nop
653
        nop
654
        nop
655
        nop
656
        nop
657
        nop
658
        nop
659
        nop
660
        nop
661
 
662
/* Level 5 */
663
        mtlr    r0
664
        lwz     r9, IP_9(r1)
665
        li      r0, PPC_IRQ_LVL5
666
        b       PROC (_ISR_Handler)
667
 
668
        nop
669
        nop
670
        nop
671
        nop
672
        nop
673
        nop
674
        nop
675
        nop
676
        nop
677
        nop
678
        nop
679
        nop
680
 
681
/* *IRQ6 */
682
        mtlr    r0
683
        lwz     r9, IP_9(r1)
684
        li      r0, PPC_IRQ_IRQ6
685
        b       PROC (_ISR_Handler)
686
 
687
        nop
688
        nop
689
        nop
690
        nop
691
        nop
692
        nop
693
        nop
694
        nop
695
        nop
696
        nop
697
        nop
698
        nop
699
 
700
/* Level 6 */
701
        mtlr    r0
702
        lwz     r9, IP_9(r1)
703
        li      r0, PPC_IRQ_LVL6
704
        b       PROC (_ISR_Handler)
705
 
706
        nop
707
        nop
708
        nop
709
        nop
710
        nop
711
        nop
712
        nop
713
        nop
714
        nop
715
        nop
716
        nop
717
        nop
718
 
719
/* *IRQ7 */
720
        mtlr    r0
721
        lwz     r9, IP_9(r1)
722
        li      r0, PPC_IRQ_IRQ7
723
        b       PROC (_ISR_Handler)
724
 
725
        nop
726
        nop
727
        nop
728
        nop
729
        nop
730
        nop
731
        nop
732
        nop
733
        nop
734
        nop
735
        nop
736
        nop
737
 
738
/* Level 7 */
739
        mtlr    r0
740
        lwz     r9, IP_9(r1)
741
        li      r0, PPC_IRQ_LVL7
742
        b       PROC (_ISR_Handler)
743
 
744
        nop
745
        nop
746
        nop
747
        nop
748
        nop
749
        nop
750
        nop
751
        nop
752
        nop
753
        nop
754
        nop
755
        nop
756
 
757
 
758
/*      .org    cpm_vector - file_base*/
759
cpm_vectors:
760
        mtlr    r0
761
        lwz     r9, IP_9(r1)
762
        li      r0, PPC_IRQ_CPM_RESERVED_0
763
        .long   0
764
 
765
        /* PC4 */
766
        mtlr    r0
767
        lwz     r9, IP_9(r1)
768
        li      r0, PPC_IRQ_CPM_PC4
769
        b       PROC (_ISR_Handler)
770
 
771
        /* PC5 */
772
        mtlr    r0
773
        lwz     r9, IP_9(r1)
774
        li      r0, PPC_IRQ_CPM_PC5
775
        b       PROC (_ISR_Handler)
776
 
777
        /* SMC2 / PIP */
778
        mtlr    r0
779
        lwz     r9, IP_9(r1)
780
        li      r0, PPC_IRQ_CPM_SMC2
781
        b       PROC (_ISR_Handler)
782
 
783
        /* SMC1 */
784
        mtlr    r0
785
        lwz     r9, IP_9(r1)
786
        li      r0, PPC_IRQ_CPM_SMC1
787
        b       PROC (_ISR_Handler)
788
 
789
        /* SPI */
790
        mtlr    r0
791
        lwz     r9, IP_9(r1)
792
        li      r0, PPC_IRQ_CPM_SPI
793
        b       PROC (_ISR_Handler)
794
 
795
        /* PC6 */
796
        mtlr    r0
797
        lwz     r9, IP_9(r1)
798
        li      r0, PPC_IRQ_CPM_PC6
799
        b       PROC (_ISR_Handler)
800
 
801
        /* Timer 4 */
802
        mtlr    r0
803
        lwz     r9, IP_9(r1)
804
        li      r0, PPC_IRQ_CPM_TIMER4
805
        b       PROC (_ISR_Handler)
806
 
807
        /* Reserved - we should never see this */
808
        mtlr    r0
809
        lwz     r9, IP_9(r1)
810
        li      r0, PPC_IRQ_CPM_RESERVED_8
811
        .long   0
812
 
813
        /* PC7 */
814
        mtlr    r0
815
        lwz     r9, IP_9(r1)
816
        li      r0, PPC_IRQ_CPM_PC7
817
        b       PROC (_ISR_Handler)
818
 
819
        /* PC8 */
820
        mtlr    r0
821
        lwz     r9, IP_9(r1)
822
        li      r0, PPC_IRQ_CPM_PC8
823
        b       PROC (_ISR_Handler)
824
 
825
        /* PC9 */
826
        mtlr    r0
827
        lwz     r9, IP_9(r1)
828
        li      r0, PPC_IRQ_CPM_PC9
829
        b       PROC (_ISR_Handler)
830
 
831
        /* Timer 3 */
832
        mtlr    r0
833
        lwz     r9, IP_9(r1)
834
        li      r0, PPC_IRQ_CPM_TIMER3
835
        b       PROC (_ISR_Handler)
836
 
837
        /* Reserved - we should never get here */
838
        mtlr    r0
839
        lwz     r9, IP_9(r1)
840
        li      r0, PPC_IRQ_CPM_RESERVED_D
841
        .long   0
842
 
843
        /* PC10 */
844
        mtlr    r0
845
        lwz     r9, IP_9(r1)
846
        li      r0, PPC_IRQ_CPM_PC10
847
        b       PROC (_ISR_Handler)
848
 
849
        /* PC11 */
850
        mtlr    r0
851
        lwz     r9, IP_9(r1)
852
        li      r0, PPC_IRQ_CPM_PC11
853
        b       PROC (_ISR_Handler)
854
 
855
        /* I2C */
856
        mtlr    r0
857
        lwz     r9, IP_9(r1)
858
        li      r0, PPC_IRQ_CPM_I2C
859
        b       PROC (_ISR_Handler)
860
 
861
        /* RISC Timer Table */
862
        mtlr    r0
863
        lwz     r9, IP_9(r1)
864
        li      r0, PPC_IRQ_CPM_RISC_TIMER
865
        b       PROC (_ISR_Handler)
866
 
867
        /* Timer 2 */
868
        mtlr    r0
869
        lwz     r9, IP_9(r1)
870
        li      r0, PPC_IRQ_CPM_TIMER2
871
        b       PROC (_ISR_Handler)
872
 
873
        /* Reserved - we should never get here */
874
        mtlr    r0
875
        lwz     r9, IP_9(r1)
876
        li      r0, PPC_IRQ_CPM_RESERVED_13
877
        .long   0
878
 
879
        /* IDMA2 */
880
        mtlr    r0
881
        lwz     r9, IP_9(r1)
882
        li      r0, PPC_IRQ_CPM_IDMA2
883
        b       PROC (_ISR_Handler)
884
 
885
        /* IDMA1 */
886
        mtlr    r0
887
        lwz     r9, IP_9(r1)
888
        li      r0, PPC_IRQ_CPM_IDMA1
889
        b       PROC (_ISR_Handler)
890
 
891
        /* SDMA Channel Bus Error */
892
        mtlr    r0
893
        lwz     r9, IP_9(r1)
894
        li      r0, PPC_IRQ_CPM_SDMA_ERROR
895
        b       PROC (_ISR_Handler)
896
 
897
        /* PC12 */
898
        mtlr    r0
899
        lwz     r9, IP_9(r1)
900
        li      r0, PPC_IRQ_CPM_PC12
901
        b       PROC (_ISR_Handler)
902
 
903
        /* PC13 */
904
        mtlr    r0
905
        lwz     r9, IP_9(r1)
906
        li      r0, PPC_IRQ_CPM_PC13
907
        b       PROC (_ISR_Handler)
908
 
909
        /* Timer 1 */
910
        mtlr    r0
911
        lwz     r9, IP_9(r1)
912
        li      r0, PPC_IRQ_CPM_TIMER1
913
        b       PROC (_ISR_Handler)
914
 
915
        /* PC14 */
916
        mtlr    r0
917
        lwz     r9, IP_9(r1)
918
        li      r0, PPC_IRQ_CPM_PC14
919
        b       PROC (_ISR_Handler)
920
 
921
        /* SCC4 */
922
        mtlr    r0
923
        lwz     r9, IP_9(r1)
924
        li      r0, PPC_IRQ_CPM_SCC4
925
        b       PROC (_ISR_Handler)
926
 
927
        /* SCC3 */
928
        mtlr    r0
929
        lwz     r9, IP_9(r1)
930
        li      r0, PPC_IRQ_CPM_SCC3
931
        b       PROC (_ISR_Handler)
932
 
933
        /* SCC2 */
934
        mtlr    r0
935
        lwz     r9, IP_9(r1)
936
        li      r0, PPC_IRQ_CPM_SCC2
937
        b       PROC (_ISR_Handler)
938
 
939
        /* SCC1 */
940
        mtlr    r0
941
        lwz     r9, IP_9(r1)
942
        li      r0, PPC_IRQ_CPM_SCC1
943
        b       PROC (_ISR_Handler)
944
 
945
        /* PC15 */
946
        mtlr    r0
947
        lwz     r9, IP_9(r1)
948
        li      r0, PPC_IRQ_CPM_PC15
949
        b       PROC (_ISR_Handler)
950
 
951
 
952
 

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