OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [powerpc/] [old_exception_processing/] [ppccache.c] - Blame information for rev 666

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  PowerPC Cache enable routines
3
 *
4
 *  $Id: ppccache.c,v 1.2 2001-09-27 12:01:29 chris Exp $
5
 */
6
 
7
#include <rtems/system.h>
8
 
9
#define PPC_Get_HID0( _value ) \
10
  do { \
11
      _value = 0;        /* to avoid warnings */ \
12
      asm volatile( \
13
          "mfspr %0, 0x3f0;"     /* get HID0 */ \
14
          "isync" \
15
          : "=r" (_value) \
16
          : "0" (_value) \
17
      ); \
18
  } while (0)
19
 
20
#define PPC_Set_HID0( _value ) \
21
  do { \
22
      asm volatile( \
23
          "isync;" \
24
          "mtspr 0x3f0, %0;"     /* load HID0 */ \
25
          "isync" \
26
          : "=r" (_value) \
27
          : "0" (_value) \
28
      ); \
29
  } while (0)
30
 
31
 
32
void powerpc_instruction_cache_enable ()
33
{
34
  unsigned32 value;
35
 
36
  /*
37
   * Enable the instruction cache
38
   */
39
 
40
  PPC_Get_HID0( value );
41
 
42
  value |= 0x00008000;       /* Set ICE bit */
43
 
44
  PPC_Set_HID0( value );
45
}
46
 
47
void powerpc_data_cache_enable ()
48
{
49
  unsigned32 value;
50
 
51
  /*
52
   * enable data cache
53
   */
54
 
55
  PPC_Get_HID0( value );
56
 
57
  value |= 0x00004000;        /* set DCE bit */
58
 
59
  PPC_Set_HID0( value );
60
}
61
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.