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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [powerpc/] [shared/] [io.h] - Blame information for rev 173

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1 30 unneback
/*
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 * io.h
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 *
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 *          This file contains inline implementation of function to
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 *          deal with IO.
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 *
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 * It is a stripped down version of linux ppc file...
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 *
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 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
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 *                     Canon Centre Recherche France.
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 *
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 *  The license and distribution terms for this file may be
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 *  found in found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: io.h,v 1.2 2001-09-27 12:01:30 chris Exp $
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 */
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#ifndef _LIBCPU_IO_H_
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#define _LIBCPU_IO_H_
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#define PREP_ISA_IO_BASE        0x80000000
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#define PREP_ISA_MEM_BASE       0xc0000000
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#define PREP_PCI_DRAM_OFFSET    0x80000000
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#define _IO_BASE        PREP_ISA_IO_BASE
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#define _ISA_MEM_BASE   PREP_ISA_MEM_BASE
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#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
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#ifndef ASM
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#define inb(port)               in_8((unsigned char *)((port)+_IO_BASE))
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#define outb(val, port)         out_8((unsigned char *)((port)+_IO_BASE), (val))
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#define inw(port)               in_le16((unsigned short *)((port)+_IO_BASE))
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#define outw(val, port)         out_le16((unsigned short *)((port)+_IO_BASE), (val))
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#define inl(port)               in_le32((unsigned *)((port)+_IO_BASE))
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#define outl(val, port)         out_le32((unsigned *)((port)+_IO_BASE), (val))
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/*
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 * Enforce In-order Execution of I/O:
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 * Acts as a barrier to ensure all previous I/O accesses have
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 * completed before any further ones are issued.
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 */
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extern inline void eieio(void)
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{
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        __asm__ __volatile__ ("eieio");
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}
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/* Enforce in-order execution of data I/O.
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 * No distinction between read/write on PPC; use eieio for all three.
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 */
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#define iobarrier_rw() eieio()
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#define iobarrier_r()  eieio()
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#define iobarrier_w()  eieio()
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/*
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 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
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 */
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extern inline int in_8(volatile unsigned char *addr)
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{
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        int ret;
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        __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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        return ret;
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}
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extern inline void out_8(volatile unsigned char *addr, int val)
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{
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        __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline int in_le16(volatile unsigned short *addr)
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{
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        int ret;
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        __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
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                              "r" (addr), "m" (*addr));
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        return ret;
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}
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extern inline int in_be16(volatile unsigned short *addr)
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{
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        int ret;
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        __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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        return ret;
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}
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extern inline void out_le16(volatile unsigned short *addr, int val)
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{
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        __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
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                              "r" (val), "r" (addr));
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}
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extern inline void out_be16(volatile unsigned short *addr, int val)
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{
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        __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline unsigned in_le32(volatile unsigned *addr)
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{
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        unsigned ret;
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        __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
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                             "r" (addr), "m" (*addr));
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        return ret;
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}
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extern inline unsigned in_be32(volatile unsigned *addr)
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{
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        unsigned ret;
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        __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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        return ret;
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}
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extern inline void out_le32(volatile unsigned *addr, int val)
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{
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        __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
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                             "r" (val), "r" (addr));
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}
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extern inline void out_be32(volatile unsigned *addr, int val)
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{
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        __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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#endif /* ASM */
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#endif /* _LIBCPU_IO_H_ */

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