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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [lib/] [libcpu/] [sh/] [sh7045/] [include/] [sh7_sci.h] - Blame information for rev 30

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1 30 unneback 
/*
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 * Bit values for the serial control registers of the Hitachi SH704X
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 *
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 * From Hitachi tutorials
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 *
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 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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 *           Bernd Becker (becker@faw.uni-ulm.de)
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 *
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 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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 *
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 *
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 *  COPYRIGHT (c) 1998.
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 *  On-Line Applications Research Corporation (OAR).
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 *  Copyright assigned to U.S. Government, 1994.
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: sh7_sci.h,v 1.2 2001-09-27 12:01:39 chris Exp $
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 */
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#ifndef _sh7_sci_h
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#define _sh7_sci_h
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#include <rtems/score/iosh7045.h>
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/*
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 * Serial mode register bits
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 */
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#define SCI_SYNC_MODE               0x80
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#define SCI_SEVEN_BIT_DATA          0x40
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#define SCI_PARITY_ON               0x20
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#define SCI_ODD_PARITY              0x10
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#define SCI_STOP_BITS_2             0x08
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#define SCI_ENABLE_MULTIP           0x04
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#define SCI_PHI_64                  0x03
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#define SCI_PHI_16                  0x02
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#define SCI_PHI_4                   0x01
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#define SCI_PHI_0                   0x00
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/*
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 * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
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 */
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#define SCI_SMR                 0x00
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#define SCI_BRR                 0x01
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#define SCI_SCR                 0x02
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#define SCI_TDR                 0x03
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#define SCI_SSR                 0x04
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#define SCI_RDR                 0x05
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/*
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 * Serial control register bits
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 */
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#define SCI_TIE                 0x80    /* Transmit interrupt enable */
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#define SCI_RIE                 0x40    /* Receive interrupt enable */
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#define SCI_TE                  0x20    /* Transmit enable */
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#define SCI_RE                  0x10    /* Receive enable */
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#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
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#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
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#define SCI_CKE1                0x02    /* Clock enable 1 */
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#define SCI_CKE0                0x01    /* Clock enable 0 */
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/*
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 * Serial status register bits
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 */
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#define SCI_TDRE                0x80    /* Transmit data register empty */
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#define SCI_RDRF                0x40    /* Receive data register full */
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#define SCI_ORER                0x20    /* Overrun error */
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#define SCI_FER                 0x10    /* Framing error */
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#define SCI_PER                 0x08    /* Parity error */
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#define SCI_TEND                0x04    /* Transmit end */
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#define SCI_MPB                 0x02    /* Multiprocessor bit */
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#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
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/*
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 * INTC Priority Settings
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 */
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#define SCI0_IPMSK      0x00F0
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#define SCI0_LOWIP      0x0010
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#define SCI1_IPMSK      0x000F
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#define SCI1_LOWIP      0x0001
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#endif /* _sh7_sci_h */

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