OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [libchip/] [serial/] [sersupp.h] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  $Id: sersupp.h,v 1.2 2001-09-27 12:01:42 chris Exp $
3
 */
4
 
5
#ifndef __LIBCHIP_SERIAL_SUPPORT_h
6
#define __LIBCHIP_SERIAL_SUPPORT_h
7
 
8
int termios_baud_to_index(
9
  int termios_baud
10
);
11
 
12
int termios_baud_to_number(
13
  int termios_baud
14
);
15
 
16
boolean libchip_serial_default_probe(
17
  int minor
18
);
19
 
20
 
21
#endif
22
/* end of include file */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.