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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [libchip/] [serial/] [z85c30.c] - Blame information for rev 480

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/*
2
 *  This file contains the console driver chip level routines for the
3
 *  Zilog z85c30 chip.
4
 *
5
 *  The Zilog Z8530 is also available as:
6
 *
7
 *    + Intel 82530
8
 *    + AMD ???
9
 *
10
 *  COPYRIGHT (c) 1998 by Radstone Technology
11
 *
12
 *
13
 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY
14
 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
15
 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK
16
 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.
17
 *
18
 * You are hereby granted permission to use, copy, modify, and distribute
19
 * this file, provided that this notice, plus the above copyright notice
20
 * and disclaimer, appears in all copies. Radstone Technology will provide
21
 * no support for this code.
22
 *
23
 *  COPYRIGHT (c) 1989-1997.
24
 *  On-Line Applications Research Corporation (OAR).
25
 *  Copyright assigned to U.S. Government, 1994.
26
 *
27
 *  The license and distribution terms for this file may be
28
 *  found in the file LICENSE in this distribution or at
29
 *  http://www.OARcorp.com/rtems/license.html.
30
 *
31
 *  $Id: z85c30.c,v 1.2 2001-09-27 12:01:42 chris Exp $
32
 */
33
 
34
#include <rtems.h>
35
#include <rtems/libio.h>
36
#include <stdlib.h>
37
 
38
#include <libchip/serial.h>
39
#include "z85c30_p.h"
40
#include "sersupp.h"
41
 
42
/*
43
 * Flow control is only supported when using interrupts
44
 */
45
 
46
console_flow z85c30_flow_RTSCTS = {
47
  z85c30_negate_RTS,    /* deviceStopRemoteTx */
48
  z85c30_assert_RTS     /* deviceStartRemoteTx */
49
};
50
 
51
console_flow z85c30_flow_DTRCTS = {
52
  z85c30_negate_DTR,    /* deviceStopRemoteTx */
53
  z85c30_assert_DTR     /* deviceStartRemoteTx */
54
};
55
 
56
/*
57
 * Exported driver function table
58
 */
59
 
60
console_fns z85c30_fns = {
61
  libchip_serial_default_probe,  /* deviceProbe */
62
  z85c30_open,                   /* deviceFirstOpen */
63
  NULL,                          /* deviceLastClose */
64
  NULL,                          /* deviceRead */
65
  z85c30_write_support_int,      /* deviceWrite */
66
  z85c30_initialize_interrupts,  /* deviceInitialize */
67
  z85c30_write_polled,           /* deviceWritePolled */
68
  NULL,                          /* deviceSetAttributes */
69
  TRUE                           /* deviceOutputUsesInterrupts */
70
};
71
 
72
console_fns z85c30_fns_polled = {
73
  libchip_serial_default_probe,      /* deviceProbe */
74
  z85c30_open,                       /* deviceFirstOpen */
75
  z85c30_close,                      /* deviceLastClose */
76
  z85c30_inbyte_nonblocking_polled,  /* deviceRead */
77
  z85c30_write_support_polled,       /* deviceWrite */
78
  z85c30_init,                       /* deviceInitialize */
79
  z85c30_write_polled,               /* deviceWritePolled */
80
  NULL,                              /* deviceSetAttributes */
81
  FALSE                              /* deviceOutputUsesInterrupts */
82
};
83
 
84
extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
85
 
86
/*
87
 *  z85c30_initialize_port
88
 *
89
 *  initialize a z85c30 Port
90
 */
91
 
92
Z85C30_STATIC void z85c30_initialize_port(
93
  int minor
94
)
95
{
96
  unsigned32      ulCtrlPort;
97
  unsigned32      ulBaudDivisor;
98
  setRegister_f   setReg;
99
 
100
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
101
  setReg   = Console_Port_Tbl[minor].setRegister;
102
 
103
  /*
104
   * Using register 4
105
   * Set up the clock rate is 16 times the data
106
   * rate, 8 bit sync char, 1 stop bit, no parity
107
   */
108
 
109
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK );
110
 
111
  /*
112
   * Set up for 8 bits/character on receive with
113
   * receiver disable via register 3
114
   */
115
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS );
116
 
117
  /*
118
   * Set up for 8 bits/character on transmit
119
   * with transmitter disable via register 5
120
   */
121
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS );
122
 
123
  /*
124
   * Clear misc control bits
125
   */
126
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 );
127
 
128
  /*
129
   * Setup the source of the receive and xmit
130
   * clock as BRG output and the transmit clock
131
   * as the output source for TRxC pin via register 11
132
   */
133
  (*setReg)(
134
    ulCtrlPort,
135
    SCC_WR0_SEL_WR11,
136
    SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI |
137
      SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN
138
  );
139
 
140
  ulBaudDivisor = Z85C30_Baud(
141
    (unsigned32) Console_Port_Tbl[minor].ulClock,
142
    (unsigned32) Console_Port_Tbl[minor].pDeviceParams
143
  );
144
 
145
  /*
146
   * Setup the lower 8 bits time constants=1E.
147
   * If the time constans=1E, then the desire
148
   * baud rate will be equilvalent to 9600, via register 12.
149
   */
150
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
151
 
152
  /*
153
   * using register 13
154
   * Setup the upper 8 bits time constant
155
   */
156
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
157
 
158
  /*
159
   * Enable the baud rate generator enable with clock from the
160
   * SCC's PCLK input via register 14.
161
   */
162
  (*setReg)(
163
    ulCtrlPort,
164
    SCC_WR0_SEL_WR14,
165
    SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL
166
  );
167
 
168
  /*
169
   * We are only interested in CTS state changes
170
   */
171
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE );
172
 
173
  /*
174
   * Reset errors
175
   */
176
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
177
 
178
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST );
179
 
180
  /*
181
   * Enable the receiver via register 3
182
   */
183
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN );
184
 
185
  /*
186
   * Enable the transmitter pins set via register 5.
187
   */
188
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN );
189
 
190
  /*
191
   * Disable interrupts
192
   */
193
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 );
194
 
195
  /*
196
   * Reset TX CRC
197
   */
198
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC );
199
 
200
  /*
201
   * Reset interrupts
202
   */
203
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT );
204
}
205
 
206
/*
207
 *  z85c30_open
208
 */
209
 
210
Z85C30_STATIC int z85c30_open(
211
  int   major,
212
  int   minor,
213
  void *arg
214
)
215
{
216
 
217
  z85c30_initialize_port(minor);
218
 
219
  /*
220
   * Assert DTR
221
   */
222
 
223
  if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) {
224
    z85c30_assert_DTR(minor);
225
  }
226
 
227
  return(RTEMS_SUCCESSFUL);
228
}
229
 
230
/*
231
 *  z85c30_close
232
 */
233
 
234
Z85C30_STATIC int z85c30_close(
235
  int   major,
236
  int   minor,
237
  void *arg
238
)
239
{
240
  /*
241
   * Negate DTR
242
   */
243
 
244
  if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) {
245
    z85c30_negate_DTR(minor);
246
  }
247
 
248
  return(RTEMS_SUCCESSFUL);
249
}
250
 
251
/*
252
 *  z85c30_init
253
 */
254
 
255
Z85C30_STATIC void z85c30_init(int minor)
256
{
257
  unsigned32       ulCtrlPort;
258
  unsigned8        dummy;
259
  z85c30_context  *pz85c30Context;
260
  setRegister_f    setReg;
261
  getRegister_f    getReg;
262
 
263
  setReg = Console_Port_Tbl[minor].setRegister;
264
  getReg   = Console_Port_Tbl[minor].getRegister;
265
 
266
  pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context));
267
 
268
  Console_Port_Data[minor].pDeviceContext = (void *)pz85c30Context;
269
 
270
  pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN;
271
 
272
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
273
  if ( ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2 ) {
274
    /*
275
     * This is channel A
276
     */
277
    /*
278
     * Ensure port state machine is reset
279
     */
280
    dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
281
 
282
    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST);
283
 
284
  } else {
285
    /*
286
     * This is channel B
287
     */
288
    /*
289
     * Ensure port state machine is reset
290
     */
291
    dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
292
 
293
    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST);
294
  }
295
}
296
 
297
/*
298
 * These routines provide control of the RTS and DTR lines
299
 */
300
 
301
/*
302
 *  z85c30_assert_RTS
303
 */
304
 
305
Z85C30_STATIC int z85c30_assert_RTS(int minor)
306
{
307
  rtems_interrupt_level  Irql;
308
  z85c30_context        *pz85c30Context;
309
  setRegister_f          setReg;
310
 
311
  setReg = Console_Port_Tbl[minor].setRegister;
312
 
313
  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
314
 
315
  /*
316
   * Assert RTS
317
   */
318
 
319
  rtems_interrupt_disable(Irql);
320
    pz85c30Context->ucModemCtrl|=SCC_WR5_RTS;
321
    (*setReg)(
322
      Console_Port_Tbl[minor].ulCtrlPort1,
323
      SCC_WR0_SEL_WR5,
324
      pz85c30Context->ucModemCtrl
325
    );
326
  rtems_interrupt_enable(Irql);
327
  return 0;
328
}
329
 
330
/*
331
 *  z85c30_negate_RTS
332
 */
333
 
334
Z85C30_STATIC int z85c30_negate_RTS(int minor)
335
{
336
  rtems_interrupt_level  Irql;
337
  z85c30_context        *pz85c30Context;
338
  setRegister_f          setReg;
339
 
340
  setReg = Console_Port_Tbl[minor].setRegister;
341
 
342
  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
343
 
344
  /*
345
   * Negate RTS
346
   */
347
 
348
  rtems_interrupt_disable(Irql);
349
    pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS;
350
    (*setReg)(
351
      Console_Port_Tbl[minor].ulCtrlPort1,
352
      SCC_WR0_SEL_WR5,
353
      pz85c30Context->ucModemCtrl
354
    );
355
  rtems_interrupt_enable(Irql);
356
  return 0;
357
}
358
 
359
/*
360
 * These flow control routines utilise a connection from the local DTR
361
 * line to the remote CTS line
362
 */
363
 
364
/*
365
 *  z85c30_assert_DTR
366
 */
367
 
368
Z85C30_STATIC int z85c30_assert_DTR(int minor)
369
{
370
  rtems_interrupt_level  Irql;
371
  z85c30_context        *pz85c30Context;
372
  setRegister_f          setReg;
373
 
374
  setReg = Console_Port_Tbl[minor].setRegister;
375
 
376
  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
377
 
378
  /*
379
   * Assert DTR
380
   */
381
 
382
  rtems_interrupt_disable(Irql);
383
    pz85c30Context->ucModemCtrl|=SCC_WR5_DTR;
384
    (*setReg)(
385
      Console_Port_Tbl[minor].ulCtrlPort1,
386
      SCC_WR0_SEL_WR5,
387
      pz85c30Context->ucModemCtrl
388
  );
389
  rtems_interrupt_enable(Irql);
390
  return 0;
391
}
392
 
393
/*
394
 *  z85c30_negate_DTR
395
 */
396
 
397
Z85C30_STATIC int z85c30_negate_DTR(int minor)
398
{
399
  rtems_interrupt_level  Irql;
400
  z85c30_context        *pz85c30Context;
401
  setRegister_f          setReg;
402
 
403
  setReg = Console_Port_Tbl[minor].setRegister;
404
 
405
  pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext;
406
 
407
  /*
408
   * Negate DTR
409
   */
410
 
411
  rtems_interrupt_disable(Irql);
412
    pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR;
413
    (*setReg)(
414
      Console_Port_Tbl[minor].ulCtrlPort1,
415
      SCC_WR0_SEL_WR5,
416
      pz85c30Context->ucModemCtrl
417
  );
418
  rtems_interrupt_enable(Irql);
419
  return 0;
420
}
421
 
422
/*
423
 *  z85c30_set_attributes
424
 *
425
 *  This function sets the SCC channel to reflect the requested termios
426
 *  port settings.
427
 */
428
 
429
Z85C30_STATIC int z85c30_set_attributes(
430
  int                   minor,
431
  const struct termios *t
432
)
433
{
434
  unsigned32             ulCtrlPort;
435
  unsigned32             ulBaudDivisor;
436
  unsigned32             wr3;
437
  unsigned32             wr4;
438
  unsigned32             wr5;
439
  int                    baud_requested;
440
  setRegister_f          setReg;
441
  rtems_interrupt_level  Irql;
442
 
443
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
444
  setReg     = Console_Port_Tbl[minor].setRegister;
445
 
446
  /*
447
   *  Calculate the baud rate divisor
448
   */
449
 
450
  baud_requested = t->c_cflag & CBAUD;
451
  if (!baud_requested)
452
    baud_requested = B9600;              /* default to 9600 baud */
453
 
454
  ulBaudDivisor = Z85C30_Baud(
455
    (unsigned32) Console_Port_Tbl[minor].ulClock,
456
    (unsigned32) termios_baud_to_number( baud_requested )
457
  );
458
 
459
  wr3 = SCC_WR3_RX_EN;
460
  wr4 = SCC_WR4_16_CLOCK;
461
  wr5 = SCC_WR5_TX_EN;
462
 
463
  /*
464
   *  Parity
465
   */
466
 
467
  if (t->c_cflag & PARENB) {
468
    wr4 |= SCC_WR4_PAR_EN;
469
    if (!(t->c_cflag & PARODD))
470
      wr4 |= SCC_WR4_PAR_EVEN;
471
  }
472
 
473
  /*
474
   *  Character Size
475
   */
476
 
477
  if (t->c_cflag & CSIZE) {
478
    switch (t->c_cflag & CSIZE) {
479
      case CS5:   break;
480
      case CS6:  wr3 |= SCC_WR3_RX_6_BITS;  wr5 |= SCC_WR5_TX_6_BITS;  break;
481
      case CS7:  wr3 |= SCC_WR3_RX_7_BITS;  wr5 |= SCC_WR5_TX_7_BITS;  break;
482
      case CS8:  wr3 |= SCC_WR3_RX_8_BITS;  wr5 |= SCC_WR5_TX_8_BITS;  break;
483
    }
484
  } else {
485
    wr3 |= SCC_WR3_RX_8_BITS;       /* default to 9600,8,N,1 */
486
    wr5 |= SCC_WR5_TX_8_BITS;       /* default to 9600,8,N,1 */
487
  }
488
 
489
  /*
490
   *  Stop Bits
491
   */
492
 
493
  if (t->c_cflag & CSTOPB) {
494
    wr4 |= SCC_WR4_2_STOP;                      /* 2 stop bits */
495
  } else {
496
    wr4 |= SCC_WR4_1_STOP;                      /* 1 stop bits */
497
  }
498
 
499
  /*
500
   *  Now actually set the chip
501
   */
502
 
503
  rtems_interrupt_disable(Irql);
504
    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 );
505
    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 );
506
    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 );
507
 
508
    /*
509
     * Setup the lower 8 bits time constants=1E.
510
     * If the time constans=1E, then the desire
511
     * baud rate will be equilvalent to 9600, via register 12.
512
     */
513
 
514
    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff );
515
 
516
    /*
517
     * using register 13
518
     * Setup the upper 8 bits time constant
519
     */
520
 
521
    (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff );
522
 
523
  rtems_interrupt_enable(Irql);
524
 
525
  return 0;
526
}
527
 
528
/*
529
 *  z85c30_process
530
 *
531
 *  This is the per port ISR handler.
532
 */
533
 
534
Z85C30_STATIC void z85c30_process(
535
  int        minor,
536
  unsigned8  ucIntPend
537
)
538
{
539
  unsigned32          ulCtrlPort;
540
  volatile unsigned8  z85c30_status;
541
  unsigned char       cChar;
542
  setRegister_f       setReg;
543
  getRegister_f       getReg;
544
 
545
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
546
  setReg     = Console_Port_Tbl[minor].setRegister;
547
  getReg     = Console_Port_Tbl[minor].getRegister;
548
 
549
  /*
550
   * Deal with any received characters
551
   */
552
 
553
  while (ucIntPend&SCC_RR3_B_RX_IP)
554
  {
555
    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
556
    if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
557
      break;
558
    }
559
 
560
    /*
561
     * Return the character read.
562
     */
563
 
564
    cChar = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
565
 
566
    rtems_termios_enqueue_raw_characters(
567
      Console_Port_Data[minor].termios_data,
568
      &cChar,
569
      1
570
    );
571
  }
572
 
573
  /*
574
   *  There could be a race condition here if there is not yet a TX
575
   *  interrupt pending but the buffer is empty.  This condition has
576
   *  been seen before on other z8530 drivers but has not been seen
577
   *  with this one.  The typical solution is to use "vector includes
578
   *  status" or to only look at the interrupts actually pending
579
   *  in RR3.
580
   */
581
 
582
  while (TRUE) {
583
    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
584
    if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
585
      /*
586
       * We'll get another interrupt when
587
       * the transmitter holding reg. becomes
588
       * free again and we are clear to send
589
       */
590
      break;
591
    }
592
 
593
#if 0
594
    if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) {
595
      /*
596
       * We can't transmit yet
597
       */
598
      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
599
      /*
600
       * The next state change of CTS will wake us up
601
       */
602
      break;
603
    }
604
#endif
605
 
606
    rtems_termios_dequeue_characters(Console_Port_Data[minor].termios_data, 1);
607
    if (rtems_termios_dequeue_characters(
608
         Console_Port_Data[minor].termios_data, 1)) {
609
      if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
610
        z85c30_negate_RTS(minor);
611
      }
612
      Console_Port_Data[minor].bActive = FALSE;
613
      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
614
      (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT);
615
      break;
616
    }
617
 
618
  }
619
 
620
  if (ucIntPend & SCC_RR3_B_EXT_IP) {
621
    /*
622
     * Clear the external status interrupt
623
     */
624
    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
625
    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
626
  }
627
 
628
  /*
629
   * Reset interrupts
630
   */
631
  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS);
632
}
633
 
634
/*
635
 *  z85c30_isr
636
 *
637
 *  This is the ISR handler for each Z8530.
638
 */
639
 
640
Z85C30_STATIC rtems_isr z85c30_isr(
641
  rtems_vector_number vector
642
)
643
{
644
  int                 minor;
645
  unsigned32          ulCtrlPort;
646
  volatile unsigned8  ucIntPend;
647
  volatile unsigned8  ucIntPendPort;
648
  getRegister_f       getReg;
649
 
650
  for (minor=0;minor<Console_Port_Count;minor++) {
651
    if(Console_Port_Tbl[minor].ulIntVector == vector &&
652
       Console_Port_Tbl[minor].deviceType == SERIAL_Z85C30 ) {
653
      ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2;
654
      getReg     = Console_Port_Tbl[minor].getRegister;
655
      do {
656
        ucIntPend = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3);
657
 
658
          /*
659
           * If this is channel A select channel A status
660
           */
661
 
662
          if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) {
663
            ucIntPendPort = ucIntPend>>3;
664
            ucIntPendPort = ucIntPendPort&=7;
665
          } else {
666
            ucIntPendPort = ucIntPend &= 7;
667
          }
668
 
669
          if (ucIntPendPort) {
670
            z85c30_process(minor, ucIntPendPort);
671
          }
672
      } while (ucIntPendPort);
673
    }
674
  }
675
}
676
 
677
/*
678
 *  z85c30_enable_interrupts
679
 *
680
 *  This routine enables the specified interrupts for this minor.
681
 */
682
 
683
Z85C30_STATIC void z85c30_enable_interrupts(
684
  int minor,
685
  int interrupt_mask
686
)
687
{
688
  unsigned32     ulCtrlPort;
689
  setRegister_f  setReg;
690
 
691
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
692
  setReg     = Console_Port_Tbl[minor].setRegister;
693
 
694
  (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR1, interrupt_mask);
695
}
696
 
697
/*
698
 *  z85c30_initialize_interrupts
699
 *
700
 *  This routine initializes the port to use interrupts.
701
 */
702
 
703
Z85C30_STATIC void z85c30_initialize_interrupts(
704
  int minor
705
)
706
{
707
  unsigned32     ulCtrlPort1;
708
  unsigned32     ulCtrlPort2;
709
  setRegister_f  setReg;
710
 
711
  ulCtrlPort1 = Console_Port_Tbl[minor].ulCtrlPort1;
712
  ulCtrlPort2 = Console_Port_Tbl[minor].ulCtrlPort2;
713
  setReg      = Console_Port_Tbl[minor].setRegister;
714
 
715
 
716
  z85c30_init(minor);
717
 
718
  Console_Port_Data[minor].bActive=FALSE;
719
 
720
  z85c30_initialize_port( minor );
721
 
722
  if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
723
    z85c30_negate_RTS(minor);
724
  }
725
 
726
  set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1);
727
 
728
  z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR_EXCEPT_TX);
729
 
730
  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR2, 0);              /* XXX vector */
731
  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR9, SCC_WR9_MIE);
732
 
733
  /*
734
   * Reset interrupts
735
   */
736
 
737
  (*setReg)(ulCtrlPort1, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT);
738
}
739
 
740
/*
741
 *  z85c30_write_support_int
742
 *
743
 *  Console Termios output entry point.
744
 *
745
 */
746
 
747
Z85C30_STATIC int z85c30_write_support_int(
748
  int   minor,
749
  const char *buf,
750
  int   len)
751
{
752
  unsigned32     Irql;
753
  unsigned32     ulCtrlPort;
754
  setRegister_f  setReg;
755
 
756
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
757
  setReg     = Console_Port_Tbl[minor].setRegister;
758
 
759
  /*
760
   *  We are using interrupt driven output and termios only sends us
761
   *  one character at a time.
762
   */
763
 
764
  if ( !len )
765
    return 0;
766
 
767
  /*
768
   *  Put the character out and enable interrupts if necessary.
769
   */
770
 
771
  if (Console_Port_Tbl[minor].pDeviceFlow != &z85c30_flow_RTSCTS) {
772
    z85c30_assert_RTS(minor);
773
  }
774
  rtems_interrupt_disable(Irql);
775
    if ( Console_Port_Data[minor].bActive == FALSE) {
776
      Console_Port_Data[minor].bActive = TRUE;
777
      z85c30_enable_interrupts(minor, SCC_ENABLE_ALL_INTR);
778
    }
779
    (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR8, *buf);
780
  rtems_interrupt_enable(Irql);
781
 
782
  return 1;
783
}
784
 
785
/*
786
 *  z85c30_inbyte_nonblocking_polled
787
 *
788
 *  This routine polls for a character.
789
 */
790
 
791
Z85C30_STATIC int z85c30_inbyte_nonblocking_polled(
792
  int  minor
793
)
794
{
795
  volatile unsigned8  z85c30_status;
796
  unsigned32          ulCtrlPort;
797
  getRegister_f       getReg;
798
 
799
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
800
  getReg     = Console_Port_Tbl[minor].getRegister;
801
 
802
  /*
803
   * return -1 if a character is not available.
804
   */
805
  z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
806
  if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) {
807
    return -1;
808
  }
809
 
810
  /*
811
   * Return the character read.
812
   */
813
 
814
  return (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD8);
815
}
816
 
817
/*
818
 *  z85c30_write_support_polled
819
 *
820
 *  Console Termios output entry point.
821
 *
822
 */
823
 
824
Z85C30_STATIC int z85c30_write_support_polled(
825
  int   minor,
826
  const char *buf,
827
  int   len)
828
{
829
  int nwrite=0;
830
 
831
  /*
832
   * poll each byte in the string out of the port.
833
   */
834
  while (nwrite < len) {
835
    z85c30_write_polled(minor, *buf++);
836
    nwrite++;
837
  }
838
 
839
  /*
840
   * return the number of bytes written.
841
   */
842
  return nwrite;
843
}
844
 
845
/*
846
 *  z85c30_write_polled
847
 *
848
 *  This routine transmits a character using polling.
849
 */
850
 
851
Z85C30_STATIC void z85c30_write_polled(
852
  int   minor,
853
  char  cChar
854
)
855
{
856
  volatile unsigned8 z85c30_status;
857
  unsigned32         ulCtrlPort;
858
  getRegister_f      getReg;
859
  setRegister_f      setReg;
860
 
861
  ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1;
862
  getReg     = Console_Port_Tbl[minor].getRegister;
863
  setReg     = Console_Port_Tbl[minor].setRegister;
864
 
865
  /*
866
   * Wait for the Transmit buffer to indicate that it is empty.
867
   */
868
 
869
  z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 );
870
 
871
  while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) {
872
    /*
873
     * Yield while we wait
874
     */
875
#if 0
876
    if (_System_state_Is_up(_System_state_Get())) {
877
      rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
878
    }
879
#endif
880
    z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0);
881
  }
882
 
883
  /*
884
   * Write the character.
885
   */
886
 
887
  (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR8, cChar );
888
}
889
 

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