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/*
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*-------------------------------------------------------------------
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*
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* 16550 -- header file for National Semiconducor's 16550 UART
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*
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* This file has been created by John S. Gwynne for the efi68k
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* project.
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*
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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*------------------------------------------------------------------
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*
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* $Id: 16550.h,v 1.2 2001-09-27 12:01:57 chris Exp $
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*/
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#ifndef _16550_H_
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#define _16550_H_
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/* base address is the physical location of register 0 */
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#define UART_BASE_ADDRESS 0xF0000000
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/* definitions of register addresses and associate bits */
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#define RBR (volatile unsigned char * const)(0+UART_BASE_ADDRESS)
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/* Receiver Buffer Register (w/DLAB=0)*/
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/* 8-bit data */
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#define THR (volatile unsigned char * const)(0+UART_BASE_ADDRESS)
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/* Transmitter Holding Register (w/DLAB=0) */
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/* 8-bit data */
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#define DLL (volatile unsigned char * const)(0+UART_BASE_ADDRESS)
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/* Divisor Latch (LS) (w/DLAB=1) */
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/* LSB of Divisor */
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#define DLM (volatile unsigned char * const)(1+UART_BASE_ADDRESS)
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/* Divisor Latch (MS) (w/DLAB=1) */
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/* MSB of Divisor */
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#define IER (volatile unsigned char * const)(1+UART_BASE_ADDRESS)
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/* Interrupt Enable Register (w/DLAB=0) */
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#define ERBFI 0x01 /* Enable Recv Data Available Interrupt */
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#define ETBEI 0x02 /* Enable Trans Holding Reg Empty Inter */
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#define ELSI 0x04 /* Enable Recv Line Status Interrupt */
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#define EDSSI 0x08 /* Enable Modem Status Interrupt */
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#define IIR (volatile unsigned char * const)(2+UART_BASE_ADDRESS)
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/* Interrupt Ident Register (read only) */
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#define NIP 0x01 /* No Interrupt Pending */
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#define IID_MASK 0x0e /* Interrupt ID mask */
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#define FE_MASK 0xc0 /* FIFO's Enabled */
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#define FCR (volatile unsigned char * const)(2+UART_BASE_ADDRESS)
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/* FIFO Control Register (write only) */
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#define FIFO_E 0x01 /* FIFO Enable */
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#define RFR 0x02 /* RCVR FIFO Reset */
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#define XFR 0x04 /* XMIT FIFO Reset */
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#define DMAMS 0x08 /* DMA Mode Select */
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#define RCVRTG_MASK 0xC0 /* RCVR Triger MSBit/LSBit */
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#define LCR (volatile unsigned char * const)(3+UART_BASE_ADDRESS)
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/* Line Control Register */
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#define WLS_MASK 0x03 /* Word Legth Select Mask */
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#define WL_5 0x00 /* 5 bits */
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#define WL_6 0x01 /* 6 bits */
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#define WL_7 0x02 /* 7 bits */
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#define WL_8 0x03 /* 8 bits */
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#define NSB 0x04 /* Number of Stop Bits (set is 2/1.5) */
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#define PEN 0x08 /* Parity Enable */
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#define EPS 0x10 /* Even Parity Select */
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#define STP 0x20 /* Stick Parity */
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#define SETBK 0x40 /* Set Break */
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#define DLAB 0x80 /* Divisor Latch Access Bit */
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#define MCR (volatile unsigned char * const)(4+UART_BASE_ADDRESS)
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/* Modem Control Register */
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#define DTR 0x01 /* Data Terminal Ready */
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#define RTS 0x02 /* Request to Send */
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#define OUT1 0x04 /* Out 1 */
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#define OUT2 0x08 /* Out 2 */
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#define LOOP 0x10 /* Loop */
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#define LSR (volatile unsigned char * const)(5+UART_BASE_ADDRESS)
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/* Line Status Register */
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun error */
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#define PE 0x04 /* Parity error */
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#define FE 0x08 /* Framing error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* Transmitter Holding Register */
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#define TEMT 0x40 /* Transmitter Empty */
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#define RCVFIE 0x80 /* Recv FIFO Error */
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#define MDSR (volatile unsigned char * const)(6+UART_BASE_ADDRESS)
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/* Modem Status Register */
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#define DCTS 0x01 /* Delta Clear to Send */
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#define DDSR 0x02 /* Delta Data Set Ready */
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#define TERI 0x04 /* Trailing Edge Ring Indicator */
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#define DDCD 0x08 /* Delta Data Carrier Detect */
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#define CTS 0x10 /* Clear to Send */
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#define DSR 0x20 /* Data Set Ready */
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#define RI 0x40 /* Ring Indicator */
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#define DCD 0x80 /* Data Carrier Detect */
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#define SCR (volatile unsigned char * const)(7+UART_BASE_ADDRESS)
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/* Scratch Register */
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/* 8-bit register */
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#endif
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