URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [librdbg/] [src/] [powerpc/] [rdbg_cpu_asm.S] - Blame information for rev 389

Go to most recent revision | Details | Compare with Previous | View Log


/*  cpu_asm.s
 *
 *  This file contains all assembly code for the Intel i386 implementation
 *  of RDBG.
 *
 * $Id: rdbg_cpu_asm.S,v 1.2 2001-09-27 12:02:02 chris Exp $
 *
 */
 
#include 
#include 
#include 
#include 
 
        BEGIN_CODE
 
/*
 *  void copyback_data_cache_and_invalidate_instr_cache(addr, size)
 *
 *  This routine performs a copy of the data cache
 *  and invalidate the instruction cache
 */
 
        .p2align  5
        PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
 
SYM (copyback_data_cache_and_invalidate_instr_cache):
        /* make sure the data changed is in the cache */
        sync
        /* r3 address to handle, r4 length in bytes */
        addi    r6, r0, PPC_CACHE_ALIGNMENT
        /* r5 = last address to handle */
        add     r5,r3,r4
        /* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) */
        subi    r0,r6,1
        andc    r3,r3,r0
        /* R4 = R3 = copy of first address */
        mr      r4,r3
        /*
         * Copyback data cache
         */
1:      cmplw   r4,r5    /* r4 >= r5 then done */
        dcbst   0,r4     /* flush (data cache bloc store) */
        add     r4,r4,r6 /* r4 = next cache line addr */
        blt     1b       /* end r4 >= r5 then done */
        sync            /* Wait for all dcbst to complete on bus */
        /*
         * invalidate instruction cache
         */
        /* R4 = fisrt address */
        mr      r4,r3
2:      cmplw   r4,r5    /* r4 >= r5 then done */
        icbi    0,r4     /* invalidate (instruction cache bloc invalidate) */
        add     r4,r4,r6 /* r4 = next cache line addr */
        blt     2b       /* end r4 >= r5 then done */
        sync             /* Wait for all icbi to complete on bus */
        isync
        blr
 
 
/*
 * void enterRdbg(void)
 *
 * This function perform a call to the exception SYSTEM call
 * It is used :
 *   1 - in the user code, to simulate a Breakpoint.
 *       (with justSaveContext = 0)
 *   2 - in the RDBG code, to push a ctx in the list.
 *       (with justSaveContext = 1)
 *
 * In most of case, it will be use as described in 1.
 * The 2nd possibility will be used by RDBG to obtain
 * its own ctx
 */
 
        PUBLIC_VAR (enterRdbg)
 
SYM (enterRdbg):
        sc
        blr
 
END_CODE
 
END

Line No.	Rev	Author	Line
1	30	unneback	`/* cpu_asm.s`
2			`*`
3			`* This file contains all assembly code for the Intel i386 implementation`
4			`* of RDBG.`
5			`*`
6			`* $Id: rdbg_cpu_asm.S,v 1.2 2001-09-27 12:02:02 chris Exp $`
7			`*`
8			`*/`
9
10			`#include`
11			`#include`
12			`#include`
13			`#include`
14
15			`BEGIN_CODE`
16
17			`/*`
18			`* void copyback_data_cache_and_invalidate_instr_cache(addr, size)`
19			`*`
20			`* This routine performs a copy of the data cache`
21			`* and invalidate the instruction cache`
22			`*/`
23
24			`.p2align 5`
25			`PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)`
26
27			`SYM (copyback_data_cache_and_invalidate_instr_cache):`
28			`/* make sure the data changed is in the cache */`
29			`sync`
30			`/* r3 address to handle, r4 length in bytes */`
31			`addi r6, r0, PPC_CACHE_ALIGNMENT`
32			`/* r5 = last address to handle */`
33			`add r5,r3,r4`
34			`/* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) */`
35			`subi r0,r6,1`
36			`andc r3,r3,r0`
37			`/* R4 = R3 = copy of first address */`
38			`mr r4,r3`
39			`/*`
40			`* Copyback data cache`
41			`*/`
42			`1: cmplw r4,r5 /* r4 >= r5 then done */`
43			`dcbst 0,r4 /* flush (data cache bloc store) */`
44			`add r4,r4,r6 /* r4 = next cache line addr */`
45			`blt 1b /* end r4 >= r5 then done */`
46			`sync /* Wait for all dcbst to complete on bus */`
47			`/*`
48			`* invalidate instruction cache`
49			`*/`
50			`/* R4 = fisrt address */`
51			`mr r4,r3`
52			`2: cmplw r4,r5 /* r4 >= r5 then done */`
53			`icbi 0,r4 /* invalidate (instruction cache bloc invalidate) */`
54			`add r4,r4,r6 /* r4 = next cache line addr */`
55			`blt 2b /* end r4 >= r5 then done */`
56			`sync /* Wait for all icbi to complete on bus */`
57			`isync`
58			`blr`
59
60
61			`/*`
62			`* void enterRdbg(void)`
63			`*`
64			`* This function perform a call to the exception SYSTEM call`
65			`* It is used :`
66			`* 1 - in the user code, to simulate a Breakpoint.`
67			`* (with justSaveContext = 0)`
68			`* 2 - in the RDBG code, to push a ctx in the list.`
69			`* (with justSaveContext = 1)`
70			`*`
71			`* In most of case, it will be use as described in 1.`
72			`* The 2nd possibility will be used by RDBG to obtain`
73			`* its own ctx`
74			`*/`
75
76			`PUBLIC_VAR (enterRdbg)`
77
78			`SYM (enterRdbg):`
79			`sc`
80			`blr`
81
82			`END_CODE`
83
84			`END`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [librdbg/] [src/] [powerpc/] [rdbg_cpu_asm.S] - Blame information for rev 389