OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [tests/] [sptests/] [sp08/] [sp08.scn] - Blame information for rev 591

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
*** TEST 8 ***
2
TA1 - rtems_task_mode - RTEMS_ASR                  - previous mode:  00000000
3
TA1 - rtems_task_mode - RTEMS_NO_ASR               - previous mode:  00000000
4
TA1 - rtems_task_mode - RTEMS_NO_ASR               - previous mode:  00000400
5
TA1 - rtems_task_mode - RTEMS_ASR                  - previous mode:  00000400
6
TA1 - rtems_task_mode - RTEMS_NO_TIMESLICE         - previous mode:  00000000
7
TA1 - rtems_task_mode - RTEMS_TIMESLICE            - previous mode:  00000000
8
TA1 - rtems_task_mode - RTEMS_TIMESLICE            - previous mode:  00000200
9
TA1 - rtems_task_mode - RTEMS_NO_TIMESLICE         - previous mode:  00000200
10
TA1 - rtems_task_mode - RTEMS_PREEMPT              - previous mode:  00000000
11
TA1 - rtems_task_mode - RTEMS_NO_PREEMPT           - previous mode:  00000000
12
TA1 - rtems_task_mode - RTEMS_NO_PREEMPT           - previous mode:  00000100
13
TA1 - rtems_task_mode - RTEMS_PREEMPT              - previous mode:  00000100
14
TA1 - rtems_task_mode - RTEMS_INTERRUPT_LEVEL( 3 ) - previous mode:  00000000
15
TA1 - rtems_task_mode - RTEMS_INTERRUPT_LEVEL( 5 ) - previous mode:  00000003
16
TA1 - rtems_task_mode - set all modes        - previous mode:  00000005
17
TA1 - rtems_task_mode - set all modes        - previous mode:  00000703
18
TA1 - rtems_task_mode - clear all modes      - previous mode:  00000703
19
TA1 - rtems_task_mode - get current mode     - previous mode:  00000000
20
*** END OF TEST 8 ***
21
 
22
NOTE: The interrupt level lines will be different on CPUs with few levels.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.