OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [tests/] [sptests/] [sp14/] [sp14.scn] - Blame information for rev 772

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback 
*** TEST 14 ***
2 
TA1 - rtems_signal_catch - RTEMS_INTERRUPT_LEVEL( 3 )
3 
TA1 - rtems_signal_send - RTEMS_SIGNAL_16 to self
4 
ASR - ENTRY - signal => 00010000
5 
ASR - EXIT  - signal => 00010000
6 
TA1 - rtems_signal_send - RTEMS_SIGNAL_0 to self
7 
ASR - ENTRY - signal => 00000001
8 
ASR - rtems_task_wake_after - yield processor
9 
TA2 - rtems_signal_send - RTEMS_SIGNAL_17 to TA1
10 
TA2 - rtems_task_wake_after - yield processor
11 
ASR - ENTRY - signal => 00020000
12 
ASR - EXIT  - signal => 00020000
13 
ASR - EXIT  - signal => 00000001
14 
TA1 - rtems_signal_catch - RTEMS_NO_ASR
15
16 
TA1 - rtems_signal_send - RTEMS_SIGNAL_1 to self
17 
ASR - ENTRY - signal => 00000002
18 
ASR - rtems_task_wake_after - yield processor
19 
TA2 - rtems_signal_send - RTEMS_SIGNAL_18 and RTEMS_SIGNAL_19 to TA1
20 
TA2 - rtems_task_wake_after - yield processor
21 
ASR - EXIT  - signal => 00000002
22 
ASR - ENTRY - signal => 000c0000
23 
ASR - EXIT  - signal => 000c0000
24 
TA1 - rtems_task_mode - disable ASRs
25 
TA1 - sending signal to RTEMS_SELF from timer
26 
TA1 - waiting for signal to arrive
27 
TA1 - timer routine got the correct arguments
28 
TA1 - rtems_task_mode - enable ASRs
29 
ASR - ENTRY - signal => 00000008
30 
ASR - EXIT  - signal => 00000008
31 
TA1 - rtems_signal_catch - asraddr of NULL
32 
TA1 - rtems_task_delete - delete self
33 
*** END OF TEST 14 ***

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.