OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [ucos-ii/] [2.91/] [ChangeLog-OR32] - Blame information for rev 520

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 474 julius
2011-01-14  Julius Baxter  
2
        * config.mk: : Added entry point at 0x100 (decimal 256).
3
 
4 471 julius
2011-01-11  Julius Baxter  
5
        * ucos-port/: Created.
6
        * tasks/: Likewise.
7
        * ucos/os_cpu_c.c: Moved to ucos-port/
8
        * os_cpu_a.S: Moved to ucos-port/
9
        * common/cprintf_r.c: Added.
10
        * ucos-port/Makefile: Likewise.
11
        * tasks/Makefile: Likewise.
12
        * include/cprintf_r.h: Likewise.
13
        * drivers/console.c: Likewise.
14
        * include/console.h: Likewise.
15
        * tasks/tasks1.c: Likewise
16
        * common/main.c:
17
        (TaskStart): Added - calls hook for tasks code TaskStartCreateTasks.
18
        (main): Changed printf to console_puts calls with loc. info.
19
        * include/spr_defs: Removed.
20
        * include/spr-defs: Added from latest or1ksim version.
21
 
22
 
23
2011-01-07  Julius Baxter  
24
        * ChangeLog-OR32: Created
25
        * sim.cfg: MC disabled, flash memory removed, MMUs disabled, debug
26
        disabled, CUC removed.
27
        * os_cpu_a.S:   Updated
28
        * ram.ld: Added
29
        * flash.ld: removed
30
        * Makefile: Final link stage replaced with $(CC) instead of $(LD), it
31
        finds libraries with greater ease.
32
        * include/board.h: Removed all MC defines, flash boot options.
33
        * include/os_cfg.h: Updated to version 2.91 (is default)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.