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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [ucos-ii/] [2.91/] [ram.ld] - Blame information for rev 647

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Line No. Rev Author Line
1 471 julius
MEMORY
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        {
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        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
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        ram     : ORIGIN = 0x00002000, LENGTH = 0x00200000 - 0x00002000
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        }
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SECTIONS
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{
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        .vectors :
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        {
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                *(.vectors)
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        } > vectors
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        .text : {
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                _stext = .;
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                *(.text)
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                _etext  =  .;
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                __CTOR_LIST__ = .;
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                LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
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                *(.ctors)
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                LONG(0)
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                __CTOR_END__ = .;
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                __DTOR_LIST__ = .;
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                LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
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                *(.dtors)
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                LONG(0)
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                __DTOR_END__ = .;
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                *(.lit)
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                *(.shdata)
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                _endtext = .;
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        }  > ram
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        .rodata : {
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                *(.rodata);
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                *(.rodata.*)
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        } > ram
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        .shbss :
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        {
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                *(.shbss)
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        } > ram
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        .talias :
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        {
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        }  > ram
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        .data : {
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                sdata  =  .;
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                _sdata  =  .;
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                *(.data)
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                edata  =  .;
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                _edata  =  .;
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        } > ram
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        .bss SIZEOF(.data) + ADDR(.data) :
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        {
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                sbss = . ;
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                _sbss = . ;
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                __bss_start = ALIGN(0x8);
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                ___bss_start = ALIGN(0x8);
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                *(.bss)
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                *(COMMON)
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                end = ALIGN(0x8);
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                _end = ALIGN(0x8);
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                __end = ALIGN(0x8);
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                ebss = .;
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                _ebss = .;
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        } > ram
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        .stack :
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        {
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        *(.stack)
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        _stack_addr = .;
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        } > ram
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}

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