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/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   nmemories = 
75
      number of memory instances connected
76
 
77
   instance specific:
78
     baseaddr = 
79
        memory start address
80
 
81
     size = 
82
        memory size
83
 
84
     name = ""
85
        memory block name
86
 
87
     ce = 
88
        chip enable index of the memory instance
89
 
90
     delayr = 
91
        cycles, required for read access, -1 if instance does not support reading
92
 
93
     delayw = 
94
        cycles, required for write access, -1 if instance does not support writing
95
 
96
     log = ""
97
        filename, where to log memory accesses to, no log, if log command is not specified
98
*/
99
 
100
section memory
101
  pattern = 0x00
102
  type = unknown /* Fastest */
103
  name = "RAM"
104
  ce = 1
105
  mc = 0
106
  baseaddr = 0x00000000
107
  size = 0x00200000
108
  delayr = 1
109
  delayw = 1
110
end
111
 
112
/* IMMU SECTION
113
 
114
    This section configures the Instruction Memory Manangement Unit
115
 
116
    enabled = 0/1
117
       '0': disabled
118
       '1': enabled
119
       (NOTE: UPR bit is set)
120
 
121
    nsets = 
122
       number of ITLB sets; must be power of two
123
 
124
    nways = 
125
       number of ITLB ways
126
 
127
    pagesize = 
128
       instruction page size; must be power of two
129
 
130
    entrysize = 
131
       instruction entry size in bytes
132
 
133
    ustates = 
134
       number of ITLB usage states (2, 3, 4 etc., max is 4)
135
 
136
    hitdelay = 
137
       number of cycles immu hit costs
138
 
139
    missdelay = 
140
       number of cycles immu miss costs
141
*/
142
 
143
section immu
144
  enabled = 0
145
  nsets = 64
146
  nways = 1
147
  pagesize = 8192
148
  hitdelay = 0
149
  missdelay = 0
150
end
151
 
152
 
153
/* DMMU SECTION
154
 
155
    This section configures the Data Memory Manangement Unit
156
 
157
    enabled = 0/1
158
       '0': disabled
159
       '1': enabled
160
       (NOTE: UPR bit is set)
161
 
162
    nsets = 
163
       number of DTLB sets; must be power of two
164
 
165
    nways = 
166
       number of DTLB ways
167
 
168
    pagesize = 
169
       data page size; must be power of two
170
 
171
    entrysize = 
172
       data entry size in bytes
173
 
174
    ustates = 
175
       number of DTLB usage states (2, 3, 4 etc., max is 4)
176
 
177
    hitdelay = 
178
       number of cycles dmmu hit costs
179
 
180
    missdelay = 
181
       number of cycles dmmu miss costs
182
*/
183
 
184
section dmmu
185
  enabled = 0
186
  nsets = 64
187
  nways = 1
188
  pagesize = 8192
189
  hitdelay = 0
190
  missdelay = 0
191
end
192
 
193
 
194
/* IC SECTION
195
 
196
   This section configures the Instruction Cache
197
 
198
   enabled = 0/1
199
       '0': disabled
200
       '1': enabled
201
      (NOTE: UPR bit is set)
202
 
203
   nsets = 
204
      number of IC sets; must be power of two
205
 
206
   nways = 
207
      number of IC ways
208
 
209
   blocksize = 
210
      IC block size in bytes; must be power of two
211
 
212
   ustates = 
213
      number of IC usage states (2, 3, 4 etc., max is 4)
214
 
215
   hitdelay = 
216
      number of cycles ic hit costs
217
 
218
    missdelay = 
219
      number of cycles ic miss costs
220
*/
221
 
222
section ic
223
  enabled = 0
224
  nsets = 256
225
  nways = 1
226
  blocksize = 16
227
  hitdelay = 0
228
  missdelay = 0
229
end
230
 
231
 
232
/* DC SECTION
233
 
234
   This section configures the Data Cache
235
 
236
   enabled = 0/1
237
       '0': disabled
238
       '1': enabled
239
      (NOTE: UPR bit is set)
240
 
241
   nsets = 
242
      number of DC sets; must be power of two
243
 
244
   nways = 
245
      number of DC ways
246
 
247
   blocksize = 
248
      DC block size in bytes; must be power of two
249
 
250
   ustates = 
251
      number of DC usage states (2, 3, 4 etc., max is 4)
252
 
253
   load_hitdelay = 
254
      number of cycles dc load hit costs
255
 
256
   load_missdelay = 
257
      number of cycles dc load miss costs
258
 
259
   store_hitdelay = 
260
      number of cycles dc load hit costs
261
 
262
   store_missdelay = 
263
      number of cycles dc load miss costs
264
*/
265
 
266
section dc
267
  enabled = 0
268
  nsets = 256
269
  nways = 1
270
  blocksize = 16
271
  load_hitdelay = 0
272
  load_missdelay = 0
273
  store_hitdelay = 0
274
  store_missdelay = 0
275
end
276
 
277
 
278
/* SIM SECTION
279
 
280
  This section specifies how or1ksim should behave.
281
 
282
  verbose = 0/1
283
       '0': don't print extra messages
284
       '1': print extra messages
285
 
286
  debug = 0-9
287
 
288
      1-9: debug message level.
289
           higher numbers produce more messages
290
 
291
  profile = 0/1
292
      '0': don't generate profiling file 'sim.profile'
293
      '1': don't generate profiling file 'sim.profile'
294
 
295
  prof_fn = ""
296
      optional filename for the profiling file.
297
      valid only if 'profile' is set
298
 
299
  mprofile = 0/1
300
      '0': don't generate memory profiling file 'sim.mprofile'
301
      '1': generate memory profiling file 'sim.mprofile'
302
 
303
  mprof_fn = ""
304
      optional filename for the memory profiling file.
305
      valid only if 'mprofile' is set
306
 
307
  history = 0/1
308
      '0': don't track execution flow
309
      '1': track execution flow
310
      Execution flow can be tracked for the simulator's
311
      'hist' command. Useful for back-trace debugging.
312
 
313
  iprompt = 0/1
314
     '0': start in  (so what do we start in ???)
315
     '1': start in interactive prompt.
316
 
317
  exe_log = 0/1
318
      '0': don't generate execution log.
319
      '1': generate execution log.
320
 
321
  exe_log_type = default/hardware/simple/software
322
      type of execution log, default is used when not specified
323
 
324
  exe_log_start = 
325
      index of first instruction to start logging, default = 0
326
 
327
  exe_log_end = 
328
      index of last instruction to end logging; not limited, if omitted
329
 
330
  exe_log_marker = 
331
       specifies number of instructions before horizontal marker is
332
      printed; if zero, markers are disabled (default)
333
 
334
  exe_log_fn = ""
335
      filename for the exection log file.
336
      valid only if 'exe_log' is set
337
 
338
  spr_log = 0/1
339
      '0': log reads/writes to/from sprs
340
      '1': don't log reads/write to/from sprs
341
 
342
  spr_log_fn = ""
343
      filename for the sprs log file.
344
      valid only if 'spr_log' is set
345
 
346
  clkcycle = [ps|ns|us|ms]
347
      specifies time measurement for one cycle
348
*/
349
 
350
section sim
351
  verbose = 0
352
  debug = 0
353
  profile = 1
354
  prof_fn = "sim.profile"
355
 
356
  mprofile = 1
357
  mprof_fn = "sim.mprofile"
358
 
359
  history = 1
360
  /* iprompt = 1 */
361
  exe_log = 0
362
  exe_log_type = software
363
  exe_log_start = 0
364
/*  exe_log_end = 20000000*/
365
  exe_log_marker = 10000
366
  exe_log_fn = "executed.log"
367
 
368
/*  spr_log = 0
369
  spr_log_fn = "spr.log"*/
370
  clkcycle = 40ns
371
end
372
 
373
 
374
/* SECTION VAPI
375
 
376
    This section configures the Verification API, used for Advanced
377
    Core Verification.
378
 
379
    enabled = 0/1
380
        '0': disbable VAPI server
381
        '1': enable/start VAPI server
382
 
383
    server_port = 
384
        TCP/IP port to start VAPI server on
385
 
386
    log_enabled = 0/1
387
       '0': disable VAPI requests logging
388
       '1': enable VAPI requests logging
389
 
390
    hide_device_id = 0/1
391
       '0': don't log device id (for compatability with old version)
392
       '1': log device id
393
 
394
 
395
    vapi_fn = 
396
       filename for the log file.
397
       valid only if log_enabled is set
398
*/
399
 
400
section VAPI
401
  enabled = 0
402
  server_port = 9998
403
  log_enabled = 0
404
  vapi_log_fn = "vapi.log"
405
end
406
 
407
 
408
/* CPU SECTION
409
 
410
   This section specifies various CPU parameters.
411
 
412
   ver = 
413
   rev = 
414
      specifies version and revision of the CPU used
415
 
416
   upr = 
417
      changes the upr register
418
 
419
   sr = 
420
      sets the initial Supervision Register value
421
 
422
   superscalar = 0/1
423
      '0': CPU is scalar
424
      '1': CPU is superscalar
425
      (modify cpu/or32/execute.c to tune superscalar model)
426
 
427
   hazards = 0/1
428
      '0': don't track data hazards in superscalar CPU
429
      '1': track data hazards in superscalar CPU
430
      If tracked, data hazards can be displayed using the
431
      simulator's 'r' command.
432
 
433
   dependstats = 0/1
434
      '0': don't calculate inter-instruction dependencies.
435
      '1': calculate inter-instruction dependencies.
436
      If calculated, inter-instruction dependencies can be
437
      displayed using the simulator's 'stat' command.
438
 
439
   sbuf_len = 
440
      length of store buffer (<= 256), 0 = disabled
441
*/
442
 
443
section cpu
444
  ver = 0x12
445
  rev = 0x01
446
  /* upr = */
447
  superscalar = 0
448
  hazards = 0
449
  dependstats = 0
450
  sbuf_len = 0
451
end
452
 
453
 
454
/* PM SECTION
455
 
456
   This section specifies Power Management parameters
457
 
458
   enabled = 0/1
459
      '0': disable power management
460
      '1': enable power management
461
*/
462
 
463
section pm
464
  enabled = 0
465
end
466
 
467
 
468
/* BPB SECTION
469
 
470
   This section specifies how branch prediction should behave.
471
 
472
   enabled = 0/1
473
     '0': disable branch prediction
474
     '1': enable branch prediction
475
 
476
   btic = 0/1
477
     '0': disable branch target instruction cache model
478
     '1': enable branch target instruction cache model
479
 
480
   sbp_bf_fwd = 0/1
481
     Static branch prediction for 'l.bf'
482
     '0': don't use forward prediction
483
     '1': use forward prediction
484
 
485
   sbp_bnf_fwd = 0/1
486
     Static branch prediction for 'l.bnf'
487
     '0': don't use forward prediction
488
     '1': use forward prediction
489
 
490
   hitdelay = 
491
       number of cycles bpb hit costs
492
 
493
   missdelay = 
494
       number of cycles bpb miss costs
495
*/
496
 
497
section bpb
498
  enabled = 0
499
  btic = 0
500
  sbp_bf_fwd = 0
501
  sbp_bnf_fwd = 0
502
  hitdelay = 0
503
  missdelay = 0
504
end
505
 
506
 
507
/* DEBUG SECTION
508
 
509
   This sections specifies how the debug unit should behave.
510
 
511
   enabled = 0/1
512
      '0': disable debug unit
513
      '1': enable debug unit
514
 
515
   gdb_enabled = 0/1
516
      '0': don't start gdb server
517
      '1': start gdb server at port 'server_port'
518
 
519
   server_port = 
520
      TCP/IP port to start gdb server on
521
      valid only if gdb_enabled is set
522
 
523
   vapi_id = 
524
      Used to create "fake" vapi log file containing the JTAG proxy messages.
525
*/
526
 
527
section debug
528
  enabled = 0
529
end
530
 
531
 
532
/* MC SECTION
533
 
534
   This section configures the memory controller
535
 
536
   enabled = 0/1
537
     '0': disable memory controller
538
     '1': enable memory controller
539
 
540
   baseaddr = 
541
      address of first MC register
542
 
543
   POC = 
544
      Power On Configuration register
545
*/
546
 
547
section mc
548
  enabled = 0
549
  baseaddr = 0x60000000
550
  POC = 0x00000008                 /* Power on configuration register */
551
end
552
 
553
 
554
/* UART SECTION
555
 
556
   This section configures the UARTs
557
 
558
   nuarts = 
559
      make specified number of instances, configure each
560
      instance within device - enddevice construct.
561
 
562
   instance specific:
563
     baseaddr = 
564
        address of first UART register for this device
565
 
566
     rxfile = ""
567
        filename, where to read data from
568
 
569
     txfile = ""
570
        filename, where to write data to
571
 
572
     irq = 
573
        irq number for this device
574
 
575
     16550 = 0/1
576
        '0': this device is a UART16450
577
        '1': this device is a UART16550
578
 
579
     jitter = 
580
        in msecs... time to block, -1 to disable it
581
 
582
     vapi_id = 
583
        VAPI id of this instance
584
*/
585
 
586
section uart
587
  baseaddr = 0x90000000
588
   irq = 2
589
    /* channel = "file:uart0.rx,uart0.tx" */
590
    /*channel = "file:/dev/tty10"*/
591
    channel = "xterm"
592
    jitter = -1                     /* async behaviour */
593
    16550 = 1
594
end
595
 
596
 
597
/* DMA SECTION
598
 
599
   This section configures the DMAs
600
 
601
   ndmas = 
602
      make specified number of instances, configure each
603
      instance within device - enddevice construct.
604
 
605
   instance specific:
606
     baseaddr = 
607
        address of first DMA register for this device
608
 
609
     irq = 
610
        irq number for this device
611
 
612
     vapi_id = 
613
        VAPI id of this instance
614
*/
615
 
616
section dma
617
  enabled = 0
618
  /*ndmas = 0
619
 
620
  device 0
621
    baseaddr = 0x9a000000
622
    irq = 11
623
  enddevice
624
  */
625
end
626
 
627
 
628
/* ETHERNET SECTION
629
 
630
   This section configures the ETHERNETs
631
 
632
   nethernets = 
633
      make specified number of instances, configure each
634
      instance within device - enddevice construct.
635
 
636
   instance specific:
637
     baseaddr = 
638
        address of first ethernet register for this device
639
 
640
     dma = 
641
        which controller is this ethernet "connected" to
642
 
643
     irq = 
644
        ethernet mac IRQ level
645
 
646
     rtx_type = 
647
        use 0 - file interface, 1 - socket interface
648
 
649
     rx_channel = 
650
        DMA channel used for RX
651
 
652
     tx_channel = 
653
        DMA channel used for TX
654
 
655
     rxfile = ""
656
        filename, where to read data from
657
 
658
     txfile = ""
659
        filename, where to write data to
660
 
661
     sockif = ""
662
        interface name of ethernet socket
663
 
664
     vapi_id = 
665
        VAPI id of this instance
666
*/
667
 
668
section ethernet
669
        enabled = 0
670
end
671
 
672
 
673
/* GPIO SECTION
674
 
675
   This section configures the GPIOs
676
 
677
   ngpios = 
678
      make specified number of instances, configure each
679
      instance within device - enddevice construct.
680
 
681
   instance specific:
682
     baseaddr = 
683
        address of first GPIO register for this device
684
 
685
     irq = 
686
        irq number for this device
687
 
688
     base_vapi_id = 
689
        first VAPI id of this instance
690
        GPIO uses 8 consecutive VAPI IDs
691
*/
692
 
693
section gpio
694
  /*ngpios = 1
695
 
696
  device 0*/
697
    enabled = 0
698
    baseaddr = 0x91000000
699
    irq = 3
700
    base_vapi_id = 0x0200
701
/*  enddevice */
702
end
703
 
704
/* VGA SECTION
705
 
706
    This section configures the VGA/LCD controller
707
 
708
    nvgas = 
709
       number of VGA devices connected
710
 
711
    instance specific:
712
      baseaddr = 
713
        address of first VGA register
714
 
715
      irq = 
716
        irq number for this device
717
 
718
      refresh_rate = 
719
        number of cycles between screen dumps
720
 
721
      filename = ""
722
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
723
*/
724
 
725
section vga
726
/*  nvgas = 1
727
 
728
  device 0 */
729
    enabled = 1
730
    baseaddr = 0x97100000
731
    irq = 8
732
    refresh_rate = 100000
733
    filename = "primary"
734
/*  enddevice */
735
end
736
 
737
 
738
/* TICK TIMER SECTION
739
 
740
    This section configures tick timer
741
 
742
    enabled = 0/1
743
      whether tick timer is enabled
744
 
745
    irq = 
746
      irq number
747
*/
748
/*
749
section tick
750
  enabled = 1
751
  irq = 0
752
end
753
*/
754
 
755
/* FB SECTION
756
 
757
    This section configures the frame buffer
758
 
759
    enabled = 0/1
760
      whether frame buffer is enabled
761
 
762
    baseaddr = 
763
      base address of frame buffer
764
 
765
    paladdr = 
766
      base address of first palette entry
767
 
768
    refresh_rate = 
769
      number of cycles between screen dumps
770
 
771
    filename = ""
772
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
773
*/
774
 
775
section fb
776
  enabled = 1
777
  baseaddr = 0x97000000
778
  refresh_rate = 1000000
779
  filename = "primary"
780
end
781
 
782
 
783
/* KBD SECTION
784
 
785
    This section configures the PS/2 compatible keyboard
786
 
787
    enabled = 0/1
788
      whether keyboard is enabled
789
 
790
    baseaddr = 
791
      base address of the keyboard device
792
 
793
    rxfile = ""
794
      filename, where to read data from
795
*/
796
 
797
section kbd
798
  enabled = 0
799
  irq = 5
800
  baseaddr = 0x94000000
801
  rxfile = "kbd.rx"
802
end
803
 
804
 
805
/* ATA SECTION
806
 
807
    This section configures the ATA/ATAPI host controller
808
 
809
    natas = 
810
       number of ATA hosts connected
811
 
812
    instance specific:
813
      baseaddr = 
814
        address of first ATA register
815
 
816
      irq = 
817
        irq number for this device
818
 
819
      debug = 
820
        debug level for ata models.
821
        0: no debug messages
822
        1: verbose messages
823
        3: normal messages (more messages than verbose)
824
        5: debug messages (normal debug messages)
825
        7: flow control messages (debug statemachine flows)
826
        9: low priority message (display everything the code does)
827
 
828
      dev_type0/1 = 
829
        ata device 0 type
830
        0: NO_CONNeCT: none (not connected)
831
        1: FILE      : simulated harddisk
832
        2: LOCAL     : local system harddisk
833
 
834
      dev_file0/1 = ""
835
        filename for simulated ATA device
836
        valid only if dev_type0 == 1
837
 
838
      dev_size0/1 = 
839
        size of simulated hard-disk (in MBytes)
840
        valid only if dev_type0 == 1
841
 
842
      dev_packet0/1 = 
843
        0: simulated ATA device does NOT implement PACKET command feature set
844
        1: simulated ATA device does implement PACKET command feature set
845
 
846
   FIXME: irq number
847
*/
848
 
849
section ata
850
/*  natas = 1
851
 
852
  device 0 */
853
    enabled = 0
854
    baseaddr = 0x9e000000
855
    irq = 15
856
 
857
/*    dev_type0   = 1
858
    dev_file0   = "/tmp/sim_atadev0"
859
    dev_size0   = 1
860
    dev_packet0 = 0
861
 
862
    dev_type1   = 0
863
    dev_file1   = ""
864
    dev_size1   = 0
865
    dev_packet1 = 0
866
  enddevice */
867
end
868
 

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