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//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's generate PC ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// PC, interface to IC. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2006/12/21 16:46:58 vak
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// Initial revision imported from
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// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
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//
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// Revision 1.10 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.9 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.7.4.3 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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//
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// Revision 1.7.4.2 2003/12/04 23:44:31 lampret
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// Static exception prefix.
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//
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// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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//
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// Revision 1.6 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.9 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_genpc(
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// Clock and reset
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clk, rst,
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// External i/f to IC
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_rty_i, icpu_adr_i,
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// Internal i/f
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, genpc_stop_prefetch, no_more_dslot
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);
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input rst;
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//
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// External i/f to IC
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//
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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input icpu_rty_i;
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input [31:0] icpu_adr_i;
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//
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// Internal i/f
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//
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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input except_prefix;
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input [31:2] branch_addrofs;
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input [31:0] lr_restor;
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input flag;
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output taken;
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input except_start;
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input [31:2] binsn_addr;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_stop_prefetch;
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input genpc_freeze;
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input no_more_dslot;
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//
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// Internal wires and regs
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//
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reg [31:2] pcreg;
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reg [31:0] pc;
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reg taken; /* Set to in case of jump or taken branch */
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reg genpc_refetch_r;
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//
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// Address of insn to be fecthed
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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//
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// Control access to IC subsystem
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//
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// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
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assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
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//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
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assign icpu_sel_o = 4'b1111;
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assign icpu_tag_o = `OR1200_ITAG_NI;
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//
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// genpc_freeze_r
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//
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always @(posedge clk or posedge rst)
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if (rst)
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genpc_refetch_r <= #1 1'b0;
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else if (genpc_refetch)
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genpc_refetch_r <= #1 1'b1;
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else
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genpc_refetch_r <= #1 1'b0;
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//
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// Async calculation of new PC value. This value is used for addressing the IC.
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//
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always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
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or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
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casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
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{2'b00, `OR1200_BRANCHOP_NOP}: begin
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pc = {pcreg + 30'd1, 2'b0};
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taken = 1'b0;
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end
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{2'b00, `OR1200_BRANCHOP_J}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
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// synopsys translate_on
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`endif
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pc = {branch_addrofs, 2'b0};
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taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_JR}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
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// synopsys translate_on
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`endif
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pc = lr_restor;
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taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_BAL}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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// synopsys translate_on
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_BF}:
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if (flag) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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// synopsys translate_on
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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taken = 1'b1;
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end
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else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BF: not taken", $time);
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// synopsys translate_on
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`endif
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pc = {pcreg + 30'd1, 2'b0};
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taken = 1'b0;
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end
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{2'b00, `OR1200_BRANCHOP_BNF}:
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if (flag) begin
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pc = {pcreg + 30'd1, 2'b0};
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: not taken", $time);
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// synopsys translate_on
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`endif
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taken = 1'b0;
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end
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else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
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// synopsys translate_on
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`endif
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pc = {binsn_addr + branch_addrofs, 2'b0};
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taken = 1'b1;
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end
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{2'b00, `OR1200_BRANCHOP_RFE}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
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// synopsys translate_on
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`endif
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pc = epcr;
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taken = 1'b1;
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end
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{2'b01, 3'bxxx}: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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`endif
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pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
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taken = 1'b1;
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end
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default: begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("l.mtspr writing into PC: %h.", spr_dat_i);
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// synopsys translate_on
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`endif
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pc = spr_dat_i;
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taken = 1'b0;
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end
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endcase
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end
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//
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// PC register
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//
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always @(posedge clk or posedge rst)
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if (rst)
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// pcreg <= #1 30'd63;
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pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
|
| 317 |
|
|
else if (spr_pc_we)
|
| 318 |
|
|
pcreg <= #1 spr_dat_i[31:2];
|
| 319 |
|
|
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
| 320 |
|
|
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
|
| 321 |
|
|
pcreg <= #1 pc[31:2];
|
| 322 |
|
|
|
| 323 |
|
|
endmodule
|
