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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of Instruction cache data rams                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2006/12/21 16:46:58  vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.6  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
// Revision 1.4  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_ic_ram(
        // Clock and reset
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_ICINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_NO_IC
 
//
// Insn cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_128x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_1024x32 ic_ram0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_2048x32 ic_ram0(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain),
        .doq(dataout)
);
 
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of Instruction cache data rams ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2006/12/21 16:46:58 vak`
48			`// Initial revision imported from`
49			`// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.`
50			`//`
51			`// Revision 1.6 2004/06/08 18:17:36 lampret`
52			`// Non-functional changes. Coding style fixes.`
53			`//`
54			`// Revision 1.5 2004/04/08 11:00:46 simont`
55			`// Add support for 512B instruction cache.`
56			`//`
57			`// Revision 1.4 2004/04/05 08:29:57 lampret`
58			`// Merged branch_qmem into main tree.`
59			`//`
60			`// Revision 1.2.4.1 2003/12/09 11:46:48 simons`
61			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
62			`//`
63			`// Revision 1.2 2002/10/17 20:04:40 lampret`
64			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
65			`//`
66			`// Revision 1.1 2002/01/03 08:16:15 lampret`
67			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
68			`//`
69			`// Revision 1.9 2001/10/21 17:57:16 lampret`
70			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
71			`//`
72			`// Revision 1.8 2001/10/14 13:12:09 lampret`
73			`// MP3 version.`
74			`//`
75			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
76			`// no message`
77			`//`
78			`// Revision 1.3 2001/08/09 13:39:33 lampret`
79			`// Major clean-up.`
80			`//`
81			`// Revision 1.2 2001/07/22 03:31:54 lampret`
82			`// Fixed RAM's oen bug. Cache bypass under development.`
83			`//`
84			`// Revision 1.1 2001/07/20 00:46:03 lampret`
85			`// Development version of RTL. Libraries are missing.`
86			`//`
87			`//`
88
89			`// synopsys translate_off`
90			`include "timescale.v"
91			`// synopsys translate_on`
92			`include "or1200_defines.v"
93
94			`module or1200_ic_ram(`
95			`// Clock and reset`
96			`clk, rst,`
97
98			`ifdef OR1200_BIST
99			`// RAM BIST`
100			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
101			`endif
102
103			`// Internal i/f`
104			`addr, en, we, datain, dataout`
105			`);`
106
107			parameter dw = `OR1200_OPERAND_WIDTH;
108			parameter aw = `OR1200_ICINDX;
109
110			`//`
111			`// I/O`
112			`//`
113			`input clk;`
114			`input rst;`
115			`input [aw-1:0] addr;`
116			`input en;`
117			`input [3:0] we;`
118			`input [dw-1:0] datain;`
119			`output [dw-1:0] dataout;`
120
121			`ifdef OR1200_BIST
122			`//`
123			`// RAM BIST`
124			`//`
125			`input mbist_si_i;`
126			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
127			`output mbist_so_o;`
128			`endif
129
130			`ifdef OR1200_NO_IC
131
132			`//`
133			`// Insn cache not implemented`
134			`//`
135			`assign dataout = {dw{1'b0}};`
136			`ifdef OR1200_BIST
137			`assign mbist_so_o = mbist_si_i;`
138			`endif
139
140			`else
141
142			`//`
143			`// Instantiation of IC RAM block`
144			`//`
145			`ifdef OR1200_IC_1W_512B
146			`or1200_spram_128x32 ic_ram0(`
147			`endif
148			`ifdef OR1200_IC_1W_4KB
149			`or1200_spram_1024x32 ic_ram0(`
150			`endif
151			`ifdef OR1200_IC_1W_8KB
152			`or1200_spram_2048x32 ic_ram0(`
153			`endif
154			`ifdef OR1200_BIST
155			`// RAM BIST`
156			`.mbist_si_i(mbist_si_i),`
157			`.mbist_so_o(mbist_so_o),`
158			`.mbist_ctrl_i(mbist_ctrl_i),`
159			`endif
160			`.clk(clk),`
161			`.rst(rst),`
162			`.ce(en),`
163			`.we(we[0]),`
164			`.oe(1'b1),`
165			`.addr(addr),`
166			`.di(datain),`
167			`.doq(dataout)`
168			`);`
169
170			`endif
171
172			`endmodule`
173

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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [or1200/] [or1200_ic_ram.v] - Blame information for rev 3