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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2006/12/21 16:46:58  vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn, if_pc, flushpipe,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
input                           flushpipe;
output                          if_stall;
input                           no_more_dslot;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
 
//
// Internal wires and regs
//
reg     [31:0]                   insn_saved;
reg     [31:0]                   addr_saved;
reg                             saved;
 
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
 
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
        if (rst)
                saved <= #1 1'b0;
        else if (flushpipe)
                saved <= #1 1'b0;
        else if (icpu_ack_i & if_freeze & !saved)
                saved <= #1 1'b1;
        else if (!if_freeze)
                saved <= #1 1'b0;
 
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
        if (rst)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else if (flushpipe)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
        else if (icpu_ack_i & if_freeze & !saved)
                insn_saved <= #1 icpu_dat_i;
        else if (!if_freeze)
                insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
 
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_saved <= #1 32'h00000000;
        else if (flushpipe)
                addr_saved <= #1 32'h00000000;
        else if (icpu_ack_i & if_freeze & !saved)
                addr_saved <= #1 icpu_adr_i;
        else if (!if_freeze)
                addr_saved <= #1 icpu_adr_i;
 
endmodule

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's instruction fetch ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, instruction fetch, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2006/12/21 16:46:58 vak`
48			`// Initial revision imported from`
49			`// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.`
50			`//`
51			`// Revision 1.5 2004/04/05 08:29:57 lampret`
52			`// Merged branch_qmem into main tree.`
53			`//`
54			`// Revision 1.3 2002/03/29 15:16:56 lampret`
55			`// Some of the warnings fixed.`
56			`//`
57			`// Revision 1.2 2002/01/28 01:16:00 lampret`
58			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
59			`//`
60			`// Revision 1.1 2002/01/03 08:16:15 lampret`
61			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
62			`//`
63			`// Revision 1.10 2001/11/20 18:46:15 simons`
64			`// Break point bug fixed`
65			`//`
66			`// Revision 1.9 2001/11/18 09:58:28 lampret`
67			`// Fixed some l.trap typos.`
68			`//`
69			`// Revision 1.8 2001/11/18 08:36:28 lampret`
70			`// For GDB changed single stepping and disabled trap exception.`
71			`//`
72			`// Revision 1.7 2001/10/21 17:57:16 lampret`
73			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
74			`//`
75			`// Revision 1.6 2001/10/14 13:12:09 lampret`
76			`// MP3 version.`
77			`//`
78			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
79			`// no message`
80			`//`
81			`// Revision 1.1 2001/08/09 13:39:33 lampret`
82			`// Major clean-up.`
83			`//`
84			`//`
85
86			`// synopsys translate_off`
87			`include "timescale.v"
88			`// synopsys translate_on`
89			`include "or1200_defines.v"
90
91			`module or1200_if(`
92			`// Clock and reset`
93			`clk, rst,`
94
95			`// External i/f to IC`
96			`icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
97
98			`// Internal i/f`
99			`if_freeze, if_insn, if_pc, flushpipe,`
100			`if_stall, no_more_dslot, genpc_refetch, rfe,`
101			`except_itlbmiss, except_immufault, except_ibuserr`
102			`);`
103
104			`//`
105			`// I/O`
106			`//`
107
108			`//`
109			`// Clock and reset`
110			`//`
111			`input clk;`
112			`input rst;`
113
114			`//`
115			`// External i/f to IC`
116			`//`
117			`input [31:0] icpu_dat_i;`
118			`input icpu_ack_i;`
119			`input icpu_err_i;`
120			`input [31:0] icpu_adr_i;`
121			`input [3:0] icpu_tag_i;`
122
123			`//`
124			`// Internal i/f`
125			`//`
126			`input if_freeze;`
127			`output [31:0] if_insn;`
128			`output [31:0] if_pc;`
129			`input flushpipe;`
130			`output if_stall;`
131			`input no_more_dslot;`
132			`output genpc_refetch;`
133			`input rfe;`
134			`output except_itlbmiss;`
135			`output except_immufault;`
136			`output except_ibuserr;`
137
138			`//`
139			`// Internal wires and regs`
140			`//`
141			`reg [31:0] insn_saved;`
142			`reg [31:0] addr_saved;`
143			`reg saved;`
144
145			`//`
146			`// IF stage insn`
147			`//`
148			assign if_insn = icpu_err_i \| no_more_dslot \| rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
149			`assign if_pc = saved ? addr_saved : icpu_adr_i;`
150			`// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;`
151			`assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;`
152			`assign genpc_refetch = saved & icpu_ack_i;`
153			assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
154			assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
155			assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
156
157			`//`
158			`// Flag for saved insn/address`
159			`//`
160			`always @(posedge clk or posedge rst)`
161			`if (rst)`
162			`saved <= #1 1'b0;`
163			`else if (flushpipe)`
164			`saved <= #1 1'b0;`
165			`else if (icpu_ack_i & if_freeze & !saved)`
166			`saved <= #1 1'b1;`
167			`else if (!if_freeze)`
168			`saved <= #1 1'b0;`
169
170			`//`
171			`// Store fetched instruction`
172			`//`
173			`always @(posedge clk or posedge rst)`
174			`if (rst)`
175			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
176			`else if (flushpipe)`
177			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
178			`else if (icpu_ack_i & if_freeze & !saved)`
179			`insn_saved <= #1 icpu_dat_i;`
180			`else if (!if_freeze)`
181			insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
182
183			`//`
184			`// Store fetched instruction's address`
185			`//`
186			`always @(posedge clk or posedge rst)`
187			`if (rst)`
188			`addr_saved <= #1 32'h00000000;`
189			`else if (flushpipe)`
190			`addr_saved <= #1 32'h00000000;`
191			`else if (icpu_ack_i & if_freeze & !saved)`
192			`addr_saved <= #1 icpu_adr_i;`
193			`else if (!if_freeze)`
194			`addr_saved <= #1 icpu_adr_i;`
195
196			`endmodule`

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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [or1200/] [or1200_if.v] - Blame information for rev 3