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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2006/12/22 08:34:00  vak
// The design is successfully compiled using on-chip RAM.
//
// Revision 1.1  2006/12/21 16:46:58  vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.11  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.1  2003/12/17 13:43:38  simons
// Exception prefix configuration changed.
//
// Revision 1.9  2002/09/07 05:42:02  lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.8  2002/08/28 01:44:25  lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.7  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.6  2002/03/11 01:26:57  lampret
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
//
// Revision 1.5  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.4  2002/01/23 07:52:36  lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3  2002/01/19 09:27:49  lampret
// SR[TEE] should be zero after reset.
//
// Revision 1.2  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/12 01:45:41  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sprs(
                // Clk & Rst
                clk, rst,
 
                // Internal CPU interface
                flagforw, flag_we, flag, cyforw, cy_we, carry,
                addrbase, addrofs, dat_i, alu_op, branch_op,
                epcr, eear, esr, except_started,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
 
                // From/to other RISC units
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                spr_addr, spr_dat_o, spr_cs, spr_we,
 
                du_addr, du_dat_du, du_read,
                du_write, du_dat_cpu
 
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O Ports
//
 
//
// Internal CPU interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           flagforw;       // From ALU
input                           flag_we;        // From ALU
output                          flag;           // SR[F]
input                           cyforw;         // From ALU
input                           cy_we;          // From ALU
output                          carry;          // SR[CY]
input   [width-1:0]              addrbase;       // SPR base address
input   [15:0]                   addrofs;        // SPR offset
input   [width-1:0]              dat_i;          // SPR write data
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;         // ALU operation
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
input   [width-1:0]              epcr;           // EPCR0
input   [width-1:0]              eear;           // EEAR0
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
input                           except_started; // Exception was started
output  [width-1:0]              to_wbmux;       // For l.mfspr
output                          epcr_we;        // EPCR0 write enable
output                          eear_we;        // EEAR0 write enable
output                          esr_we;         // ESR0 write enable
output                          pc_we;          // PC write enable
output                          sr_we;          // Write enable SR
output  [`OR1200_SR_WIDTH-1:0]   to_sr;          // Data to SR
output  [`OR1200_SR_WIDTH-1:0]   sr;             // SR
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
input   [31:0]                   spr_dat_rf;     // Data from RF
input   [31:0]                   spr_dat_npc;    // Data from NPC
input   [31:0]                   spr_dat_ppc;    // Data from PPC
input   [31:0]                   spr_dat_mac;    // Data from MAC
 
//
// To/from other RISC units
//
input   [31:0]                   spr_dat_pic;    // Data from PIC
input   [31:0]                   spr_dat_tt;     // Data from TT
input   [31:0]                   spr_dat_pm;     // Data from PM
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
input   [31:0]                   spr_dat_immu;   // Data from IMMU
input   [31:0]                   spr_dat_du;     // Data from DU
output  [31:0]                   spr_addr;       // SPR Address
output  [31:0]                   spr_dat_o;      // Data to unit
output  [31:0]                   spr_cs;         // Unit select
output                          spr_we;         // SPR write enable
 
//
// To/from Debug Unit
//
input   [width-1:0]              du_addr;        // Address
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
input                           du_read;        // Read qualifier
input                           du_write;       // Write qualifier
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
 
//
// Internal regs & wires
//
reg     [`OR1200_SR_WIDTH-1:0]           sr;             // SR
reg                             write_spr;      // Write SPR
reg                             read_spr;       // Read SPR
reg     [width-1:0]              to_wbmux;       // For l.mfspr
wire                            cfgr_sel;       // Select for cfg regs
wire                            rf_sel;         // Select for RF
wire                            npc_sel;        // Select for NPC
wire                            ppc_sel;        // Select for PPC
wire                            sr_sel;         // Select for SR
wire                            epcr_sel;       // Select for EPCR0
wire                            eear_sel;       // Select for EEAR0
wire                            esr_sel;        // Select for ESR0
wire    [31:0]                   sys_data;       // Read data from system SPRs
wire                            du_access;      // Debug unit access
wire    [`OR1200_ALUOP_WIDTH-1:0]        sprs_op;        // ALU operation
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
 
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
 
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
 
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
 
//
// SPR is written by debug unit or by l.mtspr
//
assign spr_dat_o = du_write ? du_dat_du : dat_i;
 
//
// debug unit data input:
//  - write into debug unit SPRs by debug unit itself
//  - read of SPRS by debug unit
//  - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
 
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
 
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
 
//
// Decoding of groups
//
always @(spr_addr)
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
        endcase
 
//
// SPRs System Group
//
 
//
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
                (write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
                sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_CY] =
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
                cy_we ? cyforw :
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
                sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
                flag_we ? flagforw :
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
                sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
                (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
                sr[`OR1200_SR_CE:`OR1200_SR_SM];
 
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
 
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
 
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
                  (spr_dat_rf & {32{read_spr & rf_sel}}) |
                  (spr_dat_npc & {32{read_spr & npc_sel}}) |
                  (spr_dat_ppc & {32{read_spr & ppc_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
                  (epcr & {32{read_spr & epcr_sel}}) |
                  (eear & {32{read_spr & eear_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
 
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
 
//
// Carry alias
//
assign carry = sr[`OR1200_SR_CY];
 
//
// Supervision register
//
always @(posedge clk or posedge rst)
        if (rst)
                sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
        else if (except_started) begin
                sr[`OR1200_SR_SM]  <= #1 1'b1;
                sr[`OR1200_SR_TEE] <= #1 1'b0;
                sr[`OR1200_SR_IEE] <= #1 1'b0;
                sr[`OR1200_SR_DME] <= #1 1'b0;
                sr[`OR1200_SR_IME] <= #1 1'b0;
        end
        else if (sr_we)
                sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
 
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
        case (sprs_op)  // synopsys parallel_case
                `OR1200_ALUOP_MTSR : begin
                        write_spr = 1'b1;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
                `OR1200_ALUOP_MFSR : begin
                        casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                                `OR1200_SPR_GROUP_TT:
                                        to_wbmux = spr_dat_tt;
                                `OR1200_SPR_GROUP_PIC:
                                        to_wbmux = spr_dat_pic;
                                `OR1200_SPR_GROUP_PM:
                                        to_wbmux = spr_dat_pm;
                                `OR1200_SPR_GROUP_DMMU:
                                        to_wbmux = spr_dat_dmmu;
                                `OR1200_SPR_GROUP_IMMU:
                                        to_wbmux = spr_dat_immu;
                                `OR1200_SPR_GROUP_MAC:
                                        to_wbmux = spr_dat_mac;
                                `OR1200_SPR_GROUP_DU:
                                        to_wbmux = spr_dat_du;
                                `OR1200_SPR_GROUP_SYS:
                                        to_wbmux = sys_data;
                                default:
                                        to_wbmux = 32'b0;
                        endcase
                        write_spr = 1'b0;
                        read_spr = 1'b1;
                end
                default : begin
                        write_spr = 1'b0;
                        read_spr = 1'b0;
                        to_wbmux = 32'b0;
                end
        endcase
end
 
endmodule

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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [or1200/] [or1200_sprs.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's interface to SPRs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Decoding of SPR addresses and access to SPRs ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2006/12/22 08:34:00 vak`
48			`// The design is successfully compiled using on-chip RAM.`
49			`//`
50			`// Revision 1.1 2006/12/21 16:46:58 vak`
51			`// Initial revision imported from`
52			`// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.`
53			`//`
54			`// Revision 1.11 2004/04/05 08:29:57 lampret`
55			`// Merged branch_qmem into main tree.`
56			`//`
57			`// Revision 1.9.4.1 2003/12/17 13:43:38 simons`
58			`// Exception prefix configuration changed.`
59			`//`
60			`// Revision 1.9 2002/09/07 05:42:02 lampret`
61			`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
62			`//`
63			`// Revision 1.8 2002/08/28 01:44:25 lampret`
64			`// Removed some commented RTL. Fixed SR/ESR flag bug.`
65			`//`
66			`// Revision 1.7 2002/03/29 15:16:56 lampret`
67			`// Some of the warnings fixed.`
68			`//`
69			`// Revision 1.6 2002/03/11 01:26:57 lampret`
70			`// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.`
71			`//`
72			`// Revision 1.5 2002/02/01 19:56:54 lampret`
73			`// Fixed combinational loops.`
74			`//`
75			`// Revision 1.4 2002/01/23 07:52:36 lampret`
76			`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
77			`//`
78			`// Revision 1.3 2002/01/19 09:27:49 lampret`
79			`// SR[TEE] should be zero after reset.`
80			`//`
81			`// Revision 1.2 2002/01/18 07:56:00 lampret`
82			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
83			`//`
84			`// Revision 1.1 2002/01/03 08:16:15 lampret`
85			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
86			`//`
87			`// Revision 1.12 2001/11/23 21:42:31 simons`
88			`// Program counter divided to PPC and NPC.`
89			`//`
90			`// Revision 1.11 2001/11/23 08:38:51 lampret`
91			`// Changed DSR/DRR behavior and exception detection.`
92			`//`
93			`// Revision 1.10 2001/11/12 01:45:41 lampret`
94			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
95			`//`
96			`// Revision 1.9 2001/10/21 17:57:16 lampret`
97			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
98			`//`
99			`// Revision 1.8 2001/10/14 13:12:10 lampret`
100			`// MP3 version.`
101			`//`
102			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
103			`// no message`
104			`//`
105			`// Revision 1.3 2001/08/13 03:36:20 lampret`
106			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
107			`//`
108			`// Revision 1.2 2001/08/09 13:39:33 lampret`
109			`// Major clean-up.`
110			`//`
111			`// Revision 1.1 2001/07/20 00:46:21 lampret`
112			`// Development version of RTL. Libraries are missing.`
113			`//`
114			`//`
115
116			`// synopsys translate_off`
117			`include "timescale.v"
118			`// synopsys translate_on`
119			`include "or1200_defines.v"
120
121			`module or1200_sprs(`
122			`// Clk & Rst`
123			`clk, rst,`
124
125			`// Internal CPU interface`
126			`flagforw, flag_we, flag, cyforw, cy_we, carry,`
127			`addrbase, addrofs, dat_i, alu_op, branch_op,`
128			`epcr, eear, esr, except_started,`
129			`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,`
130			`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,`
131
132			`// From/to other RISC units`
133			`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
134			`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
135			`spr_addr, spr_dat_o, spr_cs, spr_we,`
136
137			`du_addr, du_dat_du, du_read,`
138			`du_write, du_dat_cpu`
139
140			`);`
141
142			parameter width = `OR1200_OPERAND_WIDTH;
143
144			`//`
145			`// I/O Ports`
146			`//`
147
148			`//`
149			`// Internal CPU interface`
150			`//`
151			`input clk; // Clock`
152			`input rst; // Reset`
153			`input flagforw; // From ALU`
154			`input flag_we; // From ALU`
155			`output flag; // SR[F]`
156			`input cyforw; // From ALU`
157			`input cy_we; // From ALU`
158			`output carry; // SR[CY]`
159			`input [width-1:0] addrbase; // SPR base address`
160			`input [15:0] addrofs; // SPR offset`
161			`input [width-1:0] dat_i; // SPR write data`
162			input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
163			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
164			`input [width-1:0] epcr; // EPCR0`
165			`input [width-1:0] eear; // EEAR0`
166			input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
167			`input except_started; // Exception was started`
168			`output [width-1:0] to_wbmux; // For l.mfspr`
169			`output epcr_we; // EPCR0 write enable`
170			`output eear_we; // EEAR0 write enable`
171			`output esr_we; // ESR0 write enable`
172			`output pc_we; // PC write enable`
173			`output sr_we; // Write enable SR`
174			output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
175			output [`OR1200_SR_WIDTH-1:0] sr; // SR
176			`input [31:0] spr_dat_cfgr; // Data from CFGR`
177			`input [31:0] spr_dat_rf; // Data from RF`
178			`input [31:0] spr_dat_npc; // Data from NPC`
179			`input [31:0] spr_dat_ppc; // Data from PPC`
180			`input [31:0] spr_dat_mac; // Data from MAC`
181
182			`//`
183			`// To/from other RISC units`
184			`//`
185			`input [31:0] spr_dat_pic; // Data from PIC`
186			`input [31:0] spr_dat_tt; // Data from TT`
187			`input [31:0] spr_dat_pm; // Data from PM`
188			`input [31:0] spr_dat_dmmu; // Data from DMMU`
189			`input [31:0] spr_dat_immu; // Data from IMMU`
190			`input [31:0] spr_dat_du; // Data from DU`
191			`output [31:0] spr_addr; // SPR Address`
192			`output [31:0] spr_dat_o; // Data to unit`
193			`output [31:0] spr_cs; // Unit select`
194			`output spr_we; // SPR write enable`
195
196			`//`
197			`// To/from Debug Unit`
198			`//`
199			`input [width-1:0] du_addr; // Address`
200			`input [width-1:0] du_dat_du; // Data from DU to SPRS`
201			`input du_read; // Read qualifier`
202			`input du_write; // Write qualifier`
203			`output [width-1:0] du_dat_cpu; // Data from SPRS to DU`
204
205			`//`
206			`// Internal regs & wires`
207			`//`
208			reg [`OR1200_SR_WIDTH-1:0] sr; // SR
209			`reg write_spr; // Write SPR`
210			`reg read_spr; // Read SPR`
211			`reg [width-1:0] to_wbmux; // For l.mfspr`
212			`wire cfgr_sel; // Select for cfg regs`
213			`wire rf_sel; // Select for RF`
214			`wire npc_sel; // Select for NPC`
215			`wire ppc_sel; // Select for PPC`
216			`wire sr_sel; // Select for SR`
217			`wire epcr_sel; // Select for EPCR0`
218			`wire eear_sel; // Select for EEAR0`
219			`wire esr_sel; // Select for ESR0`
220			`wire [31:0] sys_data; // Read data from system SPRs`
221			`wire du_access; // Debug unit access`
222			wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
223			`reg [31:0] unqualified_cs; // Unqualified chip selects`
224
225			`//`
226			`// Decide if it is debug unit access`
227			`//`
228			`assign du_access = du_read \| du_write;`
229
230			`//`
231			`// Generate sprs opcode`
232			`//`
233			assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
234
235			`//`
236			`// Generate SPR address from base address and offset`
237			`// OR from debug unit address`
238			`//`
239			`assign spr_addr = du_access ? du_addr : addrbase \| {16'h0000, addrofs};`
240
241			`//`
242			`// SPR is written by debug unit or by l.mtspr`
243			`//`
244			`assign spr_dat_o = du_write ? du_dat_du : dat_i;`
245
246			`//`
247			`// debug unit data input:`
248			`// - write into debug unit SPRs by debug unit itself`
249			`// - read of SPRS by debug unit`
250			`// - write into debug unit SPRs by l.mtspr`
251			`//`
252			`assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;`
253
254			`//`
255			`// Write into SPRs when l.mtspr`
256			`//`
257			`assign spr_we = du_write \| write_spr;`
258
259			`//`
260			`// Qualify chip selects`
261			`//`
262			`assign spr_cs = unqualified_cs & {32{read_spr \| write_spr}};`
263
264			`//`
265			`// Decoding of groups`
266			`//`
267			`always @(spr_addr)`
268			case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
269			`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
270			`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
271			`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
272			`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
273			`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
274			`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
275			`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
276			`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
277			`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
278			`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
279			`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
280			`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
281			`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
282			`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
283			`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
284			`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
285			`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
286			`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
287			`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
288			`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
289			`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
290			`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
291			`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
292			`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
293			`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
294			`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
295			`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
296			`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
297			`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
298			`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
299			`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
300			`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
301			`endcase`
302
303			`//`
304			`// SPRs System Group`
305			`//`
306
307			`//`
308			`// What to write into SR`
309			`//`
310			assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
311			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
312			(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
313			sr[`OR1200_SR_FO:`OR1200_SR_OV];
314			assign to_sr[`OR1200_SR_CY] =
315			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
316			`cy_we ? cyforw :`
317			(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
318			sr[`OR1200_SR_CY];
319			assign to_sr[`OR1200_SR_F] =
320			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
321			`flag_we ? flagforw :`
322			(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
323			sr[`OR1200_SR_F];
324			assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
325			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
326			(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
327			sr[`OR1200_SR_CE:`OR1200_SR_SM];
328
329			`//`
330			`// Selects for system SPRs`
331			`//`
332			assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
333			assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
334			assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
335			assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
336			assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
337			assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
338			assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
339			assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
340
341			`//`
342			`// Write enables for system SPRs`
343			`//`
344			assign sr_we = (write_spr && sr_sel) \| (branch_op == `OR1200_BRANCHOP_RFE) \| flag_we \| cy_we;
345			`assign pc_we = (write_spr && (npc_sel \| ppc_sel));`
346			`assign epcr_we = (write_spr && epcr_sel);`
347			`assign eear_we = (write_spr && eear_sel);`
348			`assign esr_we = (write_spr && esr_sel);`
349
350			`//`
351			`// Output from system SPRs`
352			`//`
353			`assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) \|`
354			`(spr_dat_rf & {32{read_spr & rf_sel}}) \|`
355			`(spr_dat_npc & {32{read_spr & npc_sel}}) \|`
356			`(spr_dat_ppc & {32{read_spr & ppc_sel}}) \|`
357			({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) \|
358			`(epcr & {32{read_spr & epcr_sel}}) \|`
359			`(eear & {32{read_spr & eear_sel}}) \|`
360			({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
361
362			`//`
363			`// Flag alias`
364			`//`
365			assign flag = sr[`OR1200_SR_F];
366
367			`//`
368			`// Carry alias`
369			`//`
370			assign carry = sr[`OR1200_SR_CY];
371
372			`//`
373			`// Supervision register`
374			`//`
375			`always @(posedge clk or posedge rst)`
376			`if (rst)`
377			sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
378			`else if (except_started) begin`
379			sr[`OR1200_SR_SM] <= #1 1'b1;
380			sr[`OR1200_SR_TEE] <= #1 1'b0;
381			sr[`OR1200_SR_IEE] <= #1 1'b0;
382			sr[`OR1200_SR_DME] <= #1 1'b0;
383			sr[`OR1200_SR_IME] <= #1 1'b0;
384			`end`
385			`else if (sr_we)`
386			sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
387
388			`//`
389			`// MTSPR/MFSPR interface`
390			`//`
391			`always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or`
392			`spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin`
393			`case (sprs_op) // synopsys parallel_case`
394			`OR1200_ALUOP_MTSR : begin
395			`write_spr = 1'b1;`
396			`read_spr = 1'b0;`
397			`to_wbmux = 32'b0;`
398			`end`
399			`OR1200_ALUOP_MFSR : begin
400			casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
401			`OR1200_SPR_GROUP_TT:
402			`to_wbmux = spr_dat_tt;`
403			`OR1200_SPR_GROUP_PIC:
404			`to_wbmux = spr_dat_pic;`
405			`OR1200_SPR_GROUP_PM:
406			`to_wbmux = spr_dat_pm;`
407			`OR1200_SPR_GROUP_DMMU:
408			`to_wbmux = spr_dat_dmmu;`
409			`OR1200_SPR_GROUP_IMMU:
410			`to_wbmux = spr_dat_immu;`
411			`OR1200_SPR_GROUP_MAC:
412			`to_wbmux = spr_dat_mac;`
413			`OR1200_SPR_GROUP_DU:
414			`to_wbmux = spr_dat_du;`
415			`OR1200_SPR_GROUP_SYS:
416			`to_wbmux = sys_data;`
417			`default:`
418			`to_wbmux = 32'b0;`
419			`endcase`
420			`write_spr = 1'b0;`
421			`read_spr = 1'b1;`
422			`end`
423			`default : begin`
424			`write_spr = 1'b0;`
425			`read_spr = 1'b0;`
426			`to_wbmux = 32'b0;`
427			`end`
428			`endcase`
429			`end`
430
431			`endmodule`