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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [or1200/] [or1200_tt.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2006/12/21 16:46:58  vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4  2002/03/29 15:16:56  lampret
// Some of the warnings fixed.
//
// Revision 1.3  2002/02/12 01:33:47  lampret
// No longer using async rst as sync reset for the counter.
//
// Revision 1.2  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/13 10:00:49  lampret
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
//
// Revision 1.9  2001/11/10 03:43:57  lampret
// Fixed exceptions.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_tt(
        // RISC Internal Interface
        clk, rst, du_stall,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        intr
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           du_stall;       // DU stall
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          intr;           // Interrupt output
 
`ifdef OR1200_TT_IMPLEMENTED
 
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
`else
wire    [31:0]   ttmr;   // No TTMR register
`endif
 
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
`else
wire    [31:0]   ttcr;   // No TTCR register
`endif
 
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
always @(posedge clk or posedge rst)
        if (rst)
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
                ttmr <= #1 spr_dat_i;
        else if (ttmr[`OR1200_TT_TTMR_IE])
                ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
 
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
always @(posedge clk or posedge rst)
        if (rst)
                ttcr <= 32'b0;
        else if (restart)
                ttcr <= #1 32'b0;
        else if (ttcr_sel && spr_write)
                ttcr <= #1 spr_dat_i;
        else if (!stop)
                ttcr <= #1 ttcr + 32'd1;
`else
assign ttcr = 32'b0;
`endif
 
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
        case (spr_addr[`OR1200_TTOFS_BITS])     // synopsys parallel_case
`ifdef OR1200_TT_READREGS
                `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
                default: spr_dat_o = ttcr;
        endcase
 
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
 
//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
 
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
 
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
 
`else
 
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
 
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
 
`endif
 
endmodule

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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [or1200/] [or1200_tt.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Tick Timer ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// TT according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2006/12/21 16:46:58 vak`
48			`// Initial revision imported from`
49			`// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.`
50			`//`
51			`// Revision 1.5 2004/06/08 18:17:36 lampret`
52			`// Non-functional changes. Coding style fixes.`
53			`//`
54			`// Revision 1.4 2002/03/29 15:16:56 lampret`
55			`// Some of the warnings fixed.`
56			`//`
57			`// Revision 1.3 2002/02/12 01:33:47 lampret`
58			`// No longer using async rst as sync reset for the counter.`
59			`//`
60			`// Revision 1.2 2002/01/28 01:16:00 lampret`
61			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
62			`//`
63			`// Revision 1.1 2002/01/03 08:16:15 lampret`
64			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
65			`//`
66			`// Revision 1.10 2001/11/13 10:00:49 lampret`
67			`// Fixed tick timer interrupt reporting by using TTCR[IP] bit.`
68			`//`
69			`// Revision 1.9 2001/11/10 03:43:57 lampret`
70			`// Fixed exceptions.`
71			`//`
72			`// Revision 1.8 2001/10/21 17:57:16 lampret`
73			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
74			`//`
75			`// Revision 1.7 2001/10/14 13:12:10 lampret`
76			`// MP3 version.`
77			`//`
78			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
79			`// no message`
80			`//`
81			`// Revision 1.2 2001/08/09 13:39:33 lampret`
82			`// Major clean-up.`
83			`//`
84			`// Revision 1.1 2001/07/20 00:46:23 lampret`
85			`// Development version of RTL. Libraries are missing.`
86			`//`
87			`//`
88
89			`// synopsys translate_off`
90			`include "timescale.v"
91			`// synopsys translate_on`
92			`include "or1200_defines.v"
93
94			`module or1200_tt(`
95			`// RISC Internal Interface`
96			`clk, rst, du_stall,`
97			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
98			`intr`
99			`);`
100
101			`//`
102			`// RISC Internal Interface`
103			`//`
104			`input clk; // Clock`
105			`input rst; // Reset`
106			`input du_stall; // DU stall`
107			`input spr_cs; // SPR CS`
108			`input spr_write; // SPR Write`
109			`input [31:0] spr_addr; // SPR Address`
110			`input [31:0] spr_dat_i; // SPR Write Data`
111			`output [31:0] spr_dat_o; // SPR Read Data`
112			`output intr; // Interrupt output`
113
114			`ifdef OR1200_TT_IMPLEMENTED
115
116			`//`
117			`// TT Mode Register bits (or no register)`
118			`//`
119			`ifdef OR1200_TT_TTMR
120			`reg [31:0] ttmr; // TTMR bits`
121			`else
122			`wire [31:0] ttmr; // No TTMR register`
123			`endif
124
125			`//`
126			`// TT Count Register bits (or no register)`
127			`//`
128			`ifdef OR1200_TT_TTCR
129			`reg [31:0] ttcr; // TTCR bits`
130			`else
131			`wire [31:0] ttcr; // No TTCR register`
132			`endif
133
134			`//`
135			`// Internal wires & regs`
136			`//`
137			`wire ttmr_sel; // TTMR select`
138			`wire ttcr_sel; // TTCR select`
139			`wire match; // Asserted when TTMR[TP]`
140			`// is equal to TTCR[27:0]`
141			`wire restart; // Restart counter when asserted`
142			`wire stop; // Stop counter when asserted`
143			`reg [31:0] spr_dat_o; // SPR data out`
144
145			`//`
146			`// TT registers address decoder`
147			`//`
148			assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
149			assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
150
151			`//`
152			`// Write to TTMR or update of TTMR[IP] bit`
153			`//`
154			`ifdef OR1200_TT_TTMR
155			`always @(posedge clk or posedge rst)`
156			`if (rst)`
157			`ttmr <= 32'b0;`
158			`else if (ttmr_sel && spr_write)`
159			`ttmr <= #1 spr_dat_i;`
160			else if (ttmr[`OR1200_TT_TTMR_IE])
161			ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] \| (match & ttmr[`OR1200_TT_TTMR_IE]);
162			`else
163			`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
164			`endif
165
166			`//`
167			`// Write to or increment of TTCR`
168			`//`
169			`ifdef OR1200_TT_TTCR
170			`always @(posedge clk or posedge rst)`
171			`if (rst)`
172			`ttcr <= 32'b0;`
173			`else if (restart)`
174			`ttcr <= #1 32'b0;`
175			`else if (ttcr_sel && spr_write)`
176			`ttcr <= #1 spr_dat_i;`
177			`else if (!stop)`
178			`ttcr <= #1 ttcr + 32'd1;`
179			`else
180			`assign ttcr = 32'b0;`
181			`endif
182
183			`//`
184			`// Read TT registers`
185			`//`
186			`always @(spr_addr or ttmr or ttcr)`
187			case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
188			`ifdef OR1200_TT_READREGS
189			`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
190			`endif
191			`default: spr_dat_o = ttcr;`
192			`endcase`
193
194			`//`
195			`// A match when TTMR[TP] is equal to TTCR[27:0]`
196			`//`
197			assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
198
199			`//`
200			`// Restart when match and TTMR[M]==0x1`
201			`//`
202			assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
203
204			`//`
205			`// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit`
206			`//`
207			assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) \| (ttmr[`OR1200_TT_TTMR_M] == 2'b00) \| du_stall;
208
209			`//`
210			`// Generate an interrupt request`
211			`//`
212			assign intr = ttmr[`OR1200_TT_TTMR_IP];
213
214			`else
215
216			`//`
217			`// When TT is not implemented, drive all outputs as would when TT is disabled`
218			`//`
219			`assign intr = 1'b0;`
220
221			`//`
222			`// Read TT registers`
223			`//`
224			`ifdef OR1200_TT_READREGS
225			`assign spr_dat_o = 32'b0;`
226			`endif
227
228			`endif
229
230			`endmodule`