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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [uart16550/] [uart_tfifo.v] - Blame information for rev 3

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_tfifo.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter FIFO                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2006/12/21 16:46:58  vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15  2001/12/18 09:01:07  mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/24 08:48:10  mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:48  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
 
module uart_tfifo (clk,
        wb_rst_i, data_in, data_out,
// Control signals
        push, // push strobe, active high
        pop,   // pop strobe, active high
// status signals
        overrun,
        count,
        fifo_reset,
        reset_status
        );
 
 
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
 
input                           clk;
input                           wb_rst_i;
input                           push;
input                           pop;
input   [fifo_width-1:0] data_in;
input                           fifo_reset;
input       reset_status;
 
output  [fifo_width-1:0] data_out;
output                          overrun;
output  [fifo_counter_w-1:0]     count;
 
wire    [fifo_width-1:0] data_out;
 
// FIFO pointers
reg     [fifo_pointer_w-1:0]     top;
reg     [fifo_pointer_w-1:0]     bottom;
 
reg     [fifo_counter_w-1:0]     count;
reg                             overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
 
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
        (.clk(clk),
                        .we(push),
                        .a(top),
                        .dpra(bottom),
                        .di(data_in),
                        .dpo(data_out)
                );
 
 
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
        if (wb_rst_i)
        begin
                top             <= #1 0;
                bottom          <= #1 1'b0;
                count           <= #1 0;
        end
        else
        if (fifo_reset) begin
                top             <= #1 0;
                bottom          <= #1 1'b0;
                count           <= #1 0;
        end
  else
        begin
                case ({push, pop})
                2'b10 : if (count<fifo_depth)  // overrun condition
                        begin
                                top       <= #1 top_plus_1;
                                count     <= #1 count + 1'b1;
                        end
                2'b01 : if(count>0)
                        begin
                                bottom   <= #1 bottom + 1'b1;
                                count    <= #1 count - 1'b1;
                        end
                2'b11 : begin
                                bottom   <= #1 bottom + 1'b1;
                                top       <= #1 top_plus_1;
                        end
    default: ;
                endcase
        end
end   // always
 
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
  if (wb_rst_i)
    overrun   <= #1 1'b0;
  else
  if(fifo_reset | reset_status)
    overrun   <= #1 1'b0;
  else
  if(push & (count==fifo_depth))
    overrun   <= #1 1'b1;
end   // always
 
endmodule

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[/] [openriscdevboard/] [trunk/] [cyc2-openrisc/] [rtl/] [uart16550/] [uart_tfifo.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	sfielding	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_tfifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter FIFO ////`
19			`//// ////`
20			`//// To Do: ////`
21			`//// Nothing. ////`
22			`//// ////`
23			`//// Author(s): ////`
24			`//// - gorban@opencores.org ////`
25			`//// - Jacob Gorban ////`
26			`//// - Igor Mohor (igorm@opencores.org) ////`
27			`//// ////`
28			`//// Created: 2001/05/12 ////`
29			`//// Last Updated: 2002/07/22 ////`
30			`//// (See log for the revision history) ////`
31			`//// ////`
32			`//// ////`
33			`//////////////////////////////////////////////////////////////////////`
34			`//// ////`
35			`//// Copyright (C) 2000, 2001 Authors ////`
36			`//// ////`
37			`//// This source file may be used and distributed without ////`
38			`//// restriction provided that this copyright statement is not ////`
39			`//// removed from the file and that any derivative work contains ////`
40			`//// the original copyright notice and the associated disclaimer. ////`
41			`//// ////`
42			`//// This source file is free software; you can redistribute it ////`
43			`//// and/or modify it under the terms of the GNU Lesser General ////`
44			`//// Public License as published by the Free Software Foundation; ////`
45			`//// either version 2.1 of the License, or (at your option) any ////`
46			`//// later version. ////`
47			`//// ////`
48			`//// This source is distributed in the hope that it will be ////`
49			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
50			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
51			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
52			`//// details. ////`
53			`//// ////`
54			`//// You should have received a copy of the GNU Lesser General ////`
55			`//// Public License along with this source; if not, download it ////`
56			`//// from http://www.opencores.org/lgpl.shtml ////`
57			`//// ////`
58			`//////////////////////////////////////////////////////////////////////`
59			`//`
60			`// CVS Revision History`
61			`//`
62			`// $Log: not supported by cvs2svn $`
63			`// Revision 1.1 2006/12/21 16:46:58 vak`
64			`// Initial revision imported from`
65			`// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.`
66			`//`
67			`// Revision 1.2 2002/07/29 21:16:18 gorban`
68			`// The uart_defines.v file is included again in sources.`
69			`//`
70			`// Revision 1.1 2002/07/22 23:02:23 gorban`
71			`// Bug Fixes:`
72			`// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.`
73			`// Problem reported by Kenny.Tung.`
74			`// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.`
75			`//`
76			`// Improvements:`
77			`// * Made FIFO's as general inferrable memory where possible.`
78			`// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).`
79			`// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.`
80			`//`
81			`// * Added optional baudrate output (baud_o).`
82			`// This is identical to BAUDOUT* signal on 16550 chip.`
83			`// It outputs 16xbit_clock_rate - the divided clock.`
84			`// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.`
85			`//`
86			`// Revision 1.16 2001/12/20 13:25:46 mohor`
87			`// rx push changed to be only one cycle wide.`
88			`//`
89			`// Revision 1.15 2001/12/18 09:01:07 mohor`
90			`// Bug that was entered in the last update fixed (rx state machine).`
91			`//`
92			`// Revision 1.14 2001/12/17 14:46:48 mohor`
93			`// overrun signal was moved to separate block because many sequential lsr`
94			`// reads were preventing data from being written to rx fifo.`
95			`// underrun signal was not used and was removed from the project.`
96			`//`
97			`// Revision 1.13 2001/11/26 21:38:54 gorban`
98			`// Lots of fixes:`
99			`// Break condition wasn't handled correctly at all.`
100			`// LSR bits could lose their values.`
101			`// LSR value after reset was wrong.`
102			`// Timing of THRE interrupt signal corrected.`
103			`// LSR bit 0 timing corrected.`
104			`//`
105			`// Revision 1.12 2001/11/08 14:54:23 mohor`
106			`// Comments in Slovene language deleted, few small fixes for better work of`
107			`// old tools. IRQs need to be fix.`
108			`//`
109			`// Revision 1.11 2001/11/07 17:51:52 gorban`
110			`// Heavily rewritten interrupt and LSR subsystems.`
111			`// Many bugs hopefully squashed.`
112			`//`
113			`// Revision 1.10 2001/10/20 09:58:40 gorban`
114			`// Small synopsis fixes`
115			`//`
116			`// Revision 1.9 2001/08/24 21:01:12 mohor`
117			`// Things connected to parity changed.`
118			`// Clock devider changed.`
119			`//`
120			`// Revision 1.8 2001/08/24 08:48:10 mohor`
121			`// FIFO was not cleared after the data was read bug fixed.`
122			`//`
123			`// Revision 1.7 2001/08/23 16:05:05 mohor`
124			`// Stop bit bug fixed.`
125			`// Parity bug fixed.`
126			`// WISHBONE read cycle bug fixed,`
127			`// OE indicator (Overrun Error) bug fixed.`
128			`// PE indicator (Parity Error) bug fixed.`
129			`// Register read bug fixed.`
130			`//`
131			`// Revision 1.3 2001/05/31 20:08:01 gorban`
132			`// FIFO changes and other corrections.`
133			`//`
134			`// Revision 1.3 2001/05/27 17:37:48 gorban`
135			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
136			`//`
137			`// Revision 1.2 2001/05/17 18:34:18 gorban`
138			`// First 'stable' release. Should be sythesizable now. Also added new header.`
139			`//`
140			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
141			`// Initial revision`
142			`//`
143			`//`
144
145			`// synopsys translate_off`
146			`include "timescale.v"
147			`// synopsys translate_on`
148
149			`include "uart_defines.v"
150
151			`module uart_tfifo (clk,`
152			`wb_rst_i, data_in, data_out,`
153			`// Control signals`
154			`push, // push strobe, active high`
155			`pop, // pop strobe, active high`
156			`// status signals`
157			`overrun,`
158			`count,`
159			`fifo_reset,`
160			`reset_status`
161			`);`
162
163
164			`// FIFO parameters`
165			parameter fifo_width = `UART_FIFO_WIDTH;
166			parameter fifo_depth = `UART_FIFO_DEPTH;
167			parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
168			parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
169
170			`input clk;`
171			`input wb_rst_i;`
172			`input push;`
173			`input pop;`
174			`input [fifo_width-1:0] data_in;`
175			`input fifo_reset;`
176			`input reset_status;`
177
178			`output [fifo_width-1:0] data_out;`
179			`output overrun;`
180			`output [fifo_counter_w-1:0] count;`
181
182			`wire [fifo_width-1:0] data_out;`
183
184			`// FIFO pointers`
185			`reg [fifo_pointer_w-1:0] top;`
186			`reg [fifo_pointer_w-1:0] bottom;`
187
188			`reg [fifo_counter_w-1:0] count;`
189			`reg overrun;`
190			`wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;`
191
192			`raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo`
193			`(.clk(clk),`
194			`.we(push),`
195			`.a(top),`
196			`.dpra(bottom),`
197			`.di(data_in),`
198			`.dpo(data_out)`
199			`);`
200
201
202			`always @(posedge clk or posedge wb_rst_i) // synchronous FIFO`
203			`begin`
204			`if (wb_rst_i)`
205			`begin`
206			`top <= #1 0;`
207			`bottom <= #1 1'b0;`
208			`count <= #1 0;`
209			`end`
210			`else`
211			`if (fifo_reset) begin`
212			`top <= #1 0;`
213			`bottom <= #1 1'b0;`
214			`count <= #1 0;`
215			`end`
216			`else`
217			`begin`
218			`case ({push, pop})`
219			`2'b10 : if (count<fifo_depth) // overrun condition`
220			`begin`
221			`top <= #1 top_plus_1;`
222			`count <= #1 count + 1'b1;`
223			`end`
224			`2'b01 : if(count>0)`
225			`begin`
226			`bottom <= #1 bottom + 1'b1;`
227			`count <= #1 count - 1'b1;`
228			`end`
229			`2'b11 : begin`
230			`bottom <= #1 bottom + 1'b1;`
231			`top <= #1 top_plus_1;`
232			`end`
233			`default: ;`
234			`endcase`
235			`end`
236			`end // always`
237
238			`always @(posedge clk or posedge wb_rst_i) // synchronous FIFO`
239			`begin`
240			`if (wb_rst_i)`
241			`overrun <= #1 1'b0;`
242			`else`
243			`if(fifo_reset \| reset_status)`
244			`overrun <= #1 1'b0;`
245			`else`
246			`if(push & (count==fifo_depth))`
247			`overrun <= #1 1'b1;`
248			`end // always`
249
250			`endmodule`