URL https://opencores.org/ocsvn/opentech/opentech/trunk

Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_5_0.txt] - Blame information for rev 6

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Changes from version 1.4.1
 
OpenCores.org
======
Site and CVS are Updated
 
DESIGNS
======
- grlib library of reusable IPs (added)
- UTNios processor (added)
- Leon processor (updated)
- Handasa Arabia site (added)
- VLSI technology library (added)
- Free Model Foundation models (updated)
 
TOOLS:
=====
In instruments
- qoscc (Added)
 
In Design Entry
- gEDA (updated)
- TinyCad (added)
- xcircuit (updated)
- HDLmaker (updated)
- EDA-Index (updated)
- veditor_Eclipse (updated)
 
In DigitalDesign
- confluence (Updated)
 
In PLDs
 
 
In IC layout/vlsi
- Alliance (updated)
- electric (updated)
 
In pcb_Layout
-  Free PCB (added)
- gerv  (updated)
- PCB (updated)
 
In PIC
- KTechlab (added)
 
In Analysis
 
 
In Spice
- gnucap (updated)
 
In Simulation
- qucs (added)
- TKgate (updated)
 
In Verilog
- Ircus (updated)
- informal (added)
 
 
In Verification
- NuSMV (updated)
- Covered: Coverage Tool  (updated)
- vtracer (added)
 
- VHDL
- Alliance (updated)
- electric (updated)
- Freehdl (updated)

Line No.	Rev	Author	Line
1	6	root	`Changes from version 1.4.1`
2
3			`OpenCores.org`
4			`======`
5			`Site and CVS are Updated`
6
7			`DESIGNS`
8			`======`
9			`- grlib library of reusable IPs (added)`
10			`- UTNios processor (added)`
11			`- Leon processor (updated)`
12			`- Handasa Arabia site (added)`
13			`- VLSI technology library (added)`
14			`- Free Model Foundation models (updated)`
15
16			`TOOLS:`
17			`=====`
18			`In instruments`
19			`- qoscc (Added)`
20
21			`In Design Entry`
22			`- gEDA (updated)`
23			`- TinyCad (added)`
24			`- xcircuit (updated)`
25			`- HDLmaker (updated)`
26			`- EDA-Index (updated)`
27			`- veditor_Eclipse (updated)`
28
29			`In DigitalDesign`
30			`- confluence (Updated)`
31
32			`In PLDs`
33
34
35			`In IC layout/vlsi`
36			`- Alliance (updated)`
37			`- electric (updated)`
38
39			`In pcb_Layout`
40			`- Free PCB (added)`
41			`- gerv (updated)`
42			`- PCB (updated)`
43
44			`In PIC`
45			`- KTechlab (added)`
46
47			`In Analysis`
48
49
50			`In Spice`
51			`- gnucap (updated)`
52
53			`In Simulation`
54			`- qucs (added)`
55			`- TKgate (updated)`
56
57			`In Verilog`
58			`- Ircus (updated)`
59			`- informal (added)`
60
61
62			`In Verification`
63			`- NuSMV (updated)`
64			`- Covered: Coverage Tool (updated)`
65			`- vtracer (added)`
66
67			`- VHDL`
68			`- Alliance (updated)`
69			`- electric (updated)`
70			`- Freehdl (updated)`

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Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_5_0.txt] - Blame information for rev 6