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[/] [openverifla/] [trunk/] [openverifla_2.4/] [java/] [verifla_properties_counters.txt] - Blame information for rev 48

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# VeriFLA Logic Analyzer Project File
 
# Serial port
# On Windows this would be COM5 or similar
#/dev/ttyUSB0
LA.portName=/dev/ttyUSB0
LA.baudRate=115200
 
# Memory
# ====
LA.memWords=64
# Data input width and indentical samples bits (clones) must be multiple of 8.
LA.dataWordLenBits=16
LA.clonesWordLenBits=8
LA.triggerMatchMemAddr=8
 
 
# Generated verilog
# ====
LA.timescaleUnit=1ns
LA.timescalePrecision=10ps
# clockPeriod expressed in [timescaleUnit]
LA.clockPeriod=20
 
# User data signals
LA.totalSignals=16
# Big endian (1) or Little endian (0).
LA.signalGroups=2
# Group 0
LA.groupName.0=cnta
LA.groupSize.0=8
LA.groupEndian.0=0
# Group 1
LA.groupName.1=cntb
LA.groupSize.1=8
LA.groupEndian.1=0

Line No.	Rev	Author	Line
1	46	laurentiud	`# VeriFLA Logic Analyzer Project File`
2
3			`# Serial port`
4			`# On Windows this would be COM5 or similar`
5			`#/dev/ttyUSB0`
6			`LA.portName=/dev/ttyUSB0`
7			`LA.baudRate=115200`
8
9			`# Memory`
10			`# ====`
11			`LA.memWords=64`
12			`# Data input width and indentical samples bits (clones) must be multiple of 8.`
13			`LA.dataWordLenBits=16`
14			`LA.clonesWordLenBits=8`
15			`LA.triggerMatchMemAddr=8`
16
17
18			`# Generated verilog`
19			`# ====`
20			`LA.timescaleUnit=1ns`
21			`LA.timescalePrecision=10ps`
22			`# clockPeriod expressed in [timescaleUnit]`
23			`LA.clockPeriod=20`
24
25			`# User data signals`
26			`LA.totalSignals=16`
27			`# Big endian (1) or Little endian (0).`
28			`LA.signalGroups=2`
29			`# Group 0`
30			`LA.groupName.0=cnta`
31			`LA.groupSize.0=8`
32			`LA.groupEndian.0=0`
33			`# Group 1`
34			`LA.groupName.1=cntb`
35			`LA.groupSize.1=8`
36			`LA.groupEndian.1=0`

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[/] [openverifla/] [trunk/] [openverifla_2.4/] [java/] [verifla_properties_counters.txt] - Blame information for rev 48