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[/] [openverifla/] [trunk/] [openverifla_2.4/] [java/] [verifla_properties_counters.txt] - Blame information for rev 48

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1 46 laurentiud
# VeriFLA Logic Analyzer Project File
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# Serial port
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# On Windows this would be COM5 or similar
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#/dev/ttyUSB0
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LA.portName=/dev/ttyUSB0
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LA.baudRate=115200
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# Memory
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# ====
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LA.memWords=64
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# Data input width and indentical samples bits (clones) must be multiple of 8.
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LA.dataWordLenBits=16
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LA.clonesWordLenBits=8
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LA.triggerMatchMemAddr=8
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# Generated verilog
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# ====
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LA.timescaleUnit=1ns
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LA.timescalePrecision=10ps
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# clockPeriod expressed in [timescaleUnit]
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LA.clockPeriod=20
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# User data signals
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LA.totalSignals=16
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# Big endian (1) or Little endian (0).
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LA.signalGroups=2
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# Group 0
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LA.groupName.0=cnta
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LA.groupSize.0=8
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LA.groupEndian.0=0
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# Group 1
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LA.groupName.1=cntb
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LA.groupSize.1=8
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LA.groupEndian.1=0

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