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[/] [openverifla/] [trunk/] [openverifla_2.4/] [java/] [verifla_properties_xenomai_spi.txt] - Blame information for rev 46

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# VeriFLA Logic Analyzer Project File
 
# Serial port
# On Windows this would be COM5 or similar
#/dev/ttyUSB0
LA.portName=/dev/ttyUSB0
LA.baudRate=115200
 
# Memory
# ====
LA.memWords=128
# Data input width and indentical samples bits (clones) must be multiple of 8.
LA.dataWordLenBits=8
LA.clonesWordLenBits=8
LA.triggerMatchMemAddr=8
 
 
# Generated verilog
# ====
LA.timescaleUnit=1ns
LA.timescalePrecision=10ps
# clockPeriod expressed in [timescaleUnit]
LA.clockPeriod=20
 
# User data signals
LA.totalSignals=8
# Big endian (1) or Little endian (0).
LA.signalGroups=7
# Group 0
LA.groupName.0=MISO
LA.groupSize.0=1
LA.groupEndian.0=0
# Group 1
LA.groupName.1=MOSI
LA.groupSize.1=1
LA.groupEndian.1=0
# Group 2
LA.groupName.2=SSEL
LA.groupSize.2=1
LA.groupEndian.2=0
# Group 3
LA.groupName.3=SCK
LA.groupSize.3=1
LA.groupEndian.3=0
# Group 4
LA.groupName.4=interrupt_ack
LA.groupSize.4=1
LA.groupEndian.4=0
# Group 5
LA.groupName.5=spi_output_valid_sing
LA.groupSize.5=1
LA.groupEndian.5=0
# Group 6
LA.groupName.6=cnt
LA.groupSize.6=2
LA.groupEndian.6=0
# Group 7
#LA.groupName.7=byte_data_send
#LA.groupSize.7=8
#LA.groupEndian.7=0
# Group 8
#LA.groupName.8=spi_to_send_7_0
#LA.groupSize.8=8
#LA.groupEndian.8=0
 

Line No.	Rev	Author	Line
1	46	laurentiud	`# VeriFLA Logic Analyzer Project File`
2
3			`# Serial port`
4			`# On Windows this would be COM5 or similar`
5			`#/dev/ttyUSB0`
6			`LA.portName=/dev/ttyUSB0`
7			`LA.baudRate=115200`
8
9			`# Memory`
10			`# ====`
11			`LA.memWords=128`
12			`# Data input width and indentical samples bits (clones) must be multiple of 8.`
13			`LA.dataWordLenBits=8`
14			`LA.clonesWordLenBits=8`
15			`LA.triggerMatchMemAddr=8`
16
17
18			`# Generated verilog`
19			`# ====`
20			`LA.timescaleUnit=1ns`
21			`LA.timescalePrecision=10ps`
22			`# clockPeriod expressed in [timescaleUnit]`
23			`LA.clockPeriod=20`
24
25			`# User data signals`
26			`LA.totalSignals=8`
27			`# Big endian (1) or Little endian (0).`
28			`LA.signalGroups=7`
29			`# Group 0`
30			`LA.groupName.0=MISO`
31			`LA.groupSize.0=1`
32			`LA.groupEndian.0=0`
33			`# Group 1`
34			`LA.groupName.1=MOSI`
35			`LA.groupSize.1=1`
36			`LA.groupEndian.1=0`
37			`# Group 2`
38			`LA.groupName.2=SSEL`
39			`LA.groupSize.2=1`
40			`LA.groupEndian.2=0`
41			`# Group 3`
42			`LA.groupName.3=SCK`
43			`LA.groupSize.3=1`
44			`LA.groupEndian.3=0`
45			`# Group 4`
46			`LA.groupName.4=interrupt_ack`
47			`LA.groupSize.4=1`
48			`LA.groupEndian.4=0`
49			`# Group 5`
50			`LA.groupName.5=spi_output_valid_sing`
51			`LA.groupSize.5=1`
52			`LA.groupEndian.5=0`
53			`# Group 6`
54			`LA.groupName.6=cnt`
55			`LA.groupSize.6=2`
56			`LA.groupEndian.6=0`
57			`# Group 7`
58			`#LA.groupName.7=byte_data_send`
59			`#LA.groupSize.7=8`
60			`#LA.groupEndian.7=0`
61			`# Group 8`
62			`#LA.groupName.8=spi_to_send_7_0`
63			`#LA.groupSize.8=8`
64			`#LA.groupEndian.8=0`
65

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[/] [openverifla/] [trunk/] [openverifla_2.4/] [java/] [verifla_properties_xenomai_spi.txt] - Blame information for rev 46