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[/] [openverifla/] [trunk/] [openverifla_2.4/] [verilog/] [verifla/] [monitor_of_verifla.v] - Blame information for rev 46

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1 46 laurentiud 
/*
2 
file: monitor_of_verifla.v
3 
license: GNU GPL
4 
author: Laurentiu DUCA
5 
*/
6 
 
7 
 
8 
module monitor_of_verifla (clk, rst_l,
9 
        sys_run, user_run, data_in,
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        mem_port_A_address, mem_port_A_data_in, mem_port_A_wen,
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        ack_sc_run, sc_done, sc_run);
12 
 
13 
`include "common_internal_verifla.v"
14 
 
15 
// MON_states
16 
parameter
17 
        MON_STATES_BITS=4,
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        MON_STATE_IDLE=0,
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        MON_STATE_DO_MEM_CLEAN=1,
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        MON_STATE_PREPARE_RUN=2,
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        MON_STATE_WAIT_TRIGGER_MATCH=3,
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        MON_STATE_AFTER_TRIGGER=4,
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        MON_STATE_CLEAN_REMAINING_MEMORY1=5,
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        MON_STATE_CLEAN_REMAINING_MEMORY2=6,
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        MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS=7,
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        MON_STATE_SC_RUN=8,
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        MON_STATE_WAIT_SC_DONE=9;
28 
 
29 
// input
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input clk, rst_l;
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input [LA_DATA_INPUT_WORDLEN_BITS-1:0] data_in;
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input sys_run, user_run, ack_sc_run, sc_done;
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// output
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output [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address;
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output [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in;
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output mem_port_A_wen;
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output sc_run;
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reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address;
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reg [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in;
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reg mem_port_A_wen;
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reg sys_run_reg, sc_run, next_sc_run;
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43 
// local
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reg [MON_STATES_BITS-1:0] mon_state, next_mon_state;
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reg [LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1:0]
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        next_mon_samples_after_trigger, mon_samples_after_trigger;
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reg [LA_MEM_ADDRESS_BITS-1:0] next_mon_write_address, mon_write_address;
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reg [LA_MEM_ADDRESS_BITS-1:0] next_bt_queue_tail_address, bt_queue_tail_address;
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reg next_bt_cycled, bt_cycled;
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reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] mon_old_data_in,
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        mon_current_data_in; //={LA_DATA_INPUT_WORDLEN_BITS{1'b0}};
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reg [LA_IDENTICAL_SAMPLES_BITS-1:0] mon_clones_nr, next_mon_clones_nr;
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54 
 
55 
// Register the input data
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// such that mon_current_data_in is constant the full clock period.
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always @(posedge clk or negedge rst_l)
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begin
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        if(~rst_l)
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        begin
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                mon_old_data_in <= 0;
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                mon_current_data_in <= 0;
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                sys_run_reg <= 0;
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        end
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        else begin
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                mon_old_data_in <= mon_current_data_in;
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                mon_current_data_in <= data_in;
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                sys_run_reg <= sys_run;
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        end
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end
71 
 
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// set new values
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always @(posedge clk or negedge rst_l)
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begin
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        if(~rst_l)
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        begin
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                mon_state <= MON_STATE_IDLE;
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                sc_run <= 0;
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                mon_write_address <= LA_MEM_FIRST_ADDR;
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                bt_queue_tail_address <= 0;
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                bt_cycled <= 0;
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                mon_samples_after_trigger <= 0;
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                mon_clones_nr <= 1;
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        end
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        else begin
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                mon_state <= next_mon_state;
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                sc_run <= next_sc_run;
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                mon_write_address <= next_mon_write_address;
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                bt_queue_tail_address <= next_bt_queue_tail_address;
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                bt_cycled <= next_bt_cycled;
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                mon_samples_after_trigger <= next_mon_samples_after_trigger;
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                mon_clones_nr <= next_mon_clones_nr;
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        end
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end
95 
 
96 
 
97 
// continuous assignments
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wire [LA_MEM_ADDRESS_BITS-1:0] one_plus_mon_write_address = (mon_write_address+1);
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wire [LA_IDENTICAL_SAMPLES_BITS-1:0] oneplus_mon_clones_nr = (mon_clones_nr+1);
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wire data_in_changed = ((mon_current_data_in & LA_TRACE_MASK) != (mon_old_data_in & LA_TRACE_MASK));
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wire last_mem_addr_before_trigger = (mon_write_address == LA_MEM_LAST_ADDR_BEFORE_TRIGGER);
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wire not_maximum_mon_clones_nr = (mon_clones_nr < LA_MAX_IDENTICAL_SAMPLES);
103 
 
104 
 
105 
//  mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
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task mon_prepare_run;
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begin
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                // we share the same clock as memory.
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                mem_port_A_address=LA_MEM_FIRST_ADDR;
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                mem_port_A_data_in={{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
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                mem_port_A_wen=1;
112 
                next_mon_write_address=LA_MEM_FIRST_ADDR;
113 
                next_mon_clones_nr=2;
114 
                next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH;
115 
end
116 
endtask
117 
 
118 
 
119 
// state machine
120 
always @(*)
121 
/*
122 
        mon_state or  sys_run_reg
123 
        or ack_sc_run or sc_done or sc_run
124 
        // eliminate warnings
125 
        or mon_write_address or bt_queue_tail_address or mon_samples_after_trigger
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        or mon_current_data_in or mon_old_data_in or mon_clones_nr
127 
        or data_in_changed or oneplus_mon_clones_nr or one_plus_mon_write_address
128 
        or not_maximum_mon_clones_nr
129 
        or last_mem_addr_before_trigger)
130 
*/
131 
begin
132 
        // implicit
133 
        next_mon_state=mon_state;
134 
        next_sc_run=sc_run;
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        next_mon_write_address=mon_write_address;
136 
        next_bt_queue_tail_address=bt_queue_tail_address;
137 
        next_bt_cycled=bt_cycled;
138 
        next_mon_samples_after_trigger=mon_samples_after_trigger;
139 
        next_mon_clones_nr = mon_clones_nr;
140 
        mem_port_A_address=0;
141 
        mem_port_A_data_in=0;
142 
        mem_port_A_wen=0;
143 
 
144 
        // state dependent
145 
        case(mon_state)
146 
        MON_STATE_IDLE:
147 
        begin
148 
                next_bt_cycled = 0;
149 
                if(sys_run_reg || user_run)
150 
                begin
151 
                        if(user_run) begin
152 
                                next_mon_write_address=LA_MEM_FIRST_ADDR;
153 
                                next_mon_state=MON_STATE_DO_MEM_CLEAN;
154 
                        end else
155 
                                mon_prepare_run;
156 
                end
157 
                else
158 
                        next_mon_state=MON_STATE_IDLE;
159 
        end
160 
 
161 
        MON_STATE_DO_MEM_CLEAN:
162 
        begin
163 
                mem_port_A_address=mon_write_address;
164 
                mem_port_A_data_in=LA_MEM_EMPTY_SLOT;
165 
                mem_port_A_wen=1;
166 
                if(mon_write_address < LA_MEM_LAST_ADDR)
167 
                begin
168 
                        next_mon_write_address=mon_write_address+1;
169 
                        next_mon_state = MON_STATE_DO_MEM_CLEAN;
170 
                end
171 
                else
172 
                        // at the new posedge clock, will clean memory at its last address
173 
                        next_mon_state = MON_STATE_PREPARE_RUN;
174 
        end
175 
 
176 
        MON_STATE_PREPARE_RUN:
177 
        begin
178 
                mon_prepare_run;
179 
        end
180 
 
181 
        MON_STATE_WAIT_TRIGGER_MATCH:
182 
        begin
183 
                // circular queue
184 
                if((mon_current_data_in & LA_TRIGGER_MASK) !=
185 
                        (LA_TRIGGER_VALUE & LA_TRIGGER_MASK))
186 
                begin
187 
                        next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH;
188 
                        mem_port_A_wen = 1;
189 
                        mem_port_A_address = data_in_changed ?
190 
                                                                                        (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address) :
191 
                                                                                        (not_maximum_mon_clones_nr ? mon_write_address :
192 
                                                                                                (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address));
193 
                        mem_port_A_data_in = data_in_changed ?
194 
                                                                                        {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
195 
                                                                                        (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} :
196 
                                                                                                {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
197 
                        next_mon_clones_nr = data_in_changed ? 2 :
198 
                                                                                        (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2);
199 
                        next_mon_write_address = data_in_changed ?
200 
                                                                                        (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR: one_plus_mon_write_address) :
201 
                                                                                        (not_maximum_mon_clones_nr ? mon_write_address :
202 
                                                                                                (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address));
203 
                        if(!bt_cycled)
204 
                                next_bt_cycled = ((data_in_changed && last_mem_addr_before_trigger) ||
205 
                                        (!data_in_changed && !not_maximum_mon_clones_nr && last_mem_addr_before_trigger));
206 
                end
207 
                else begin
208 
                        // trigger matched
209 
                        next_mon_state=MON_STATE_AFTER_TRIGGER;
210 
                        mem_port_A_address=LA_TRIGGER_MATCH_MEM_ADDR;
211 
                        mem_port_A_data_in = {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, mon_current_data_in};
212 
                        mem_port_A_wen=1;
213 
                        next_mon_write_address=LA_TRIGGER_MATCH_MEM_ADDR;
214 
                        next_mon_clones_nr=2;
215 
                        next_bt_queue_tail_address = mon_write_address;
216 
                        next_mon_samples_after_trigger=1;
217 
                end
218 
        end
219 
 
220 
        MON_STATE_AFTER_TRIGGER:
221 
        begin
222 
                if((mon_samples_after_trigger < LA_MAX_SAMPLES_AFTER_TRIGGER) &&
223 
                        (mon_write_address < LA_MEM_LAST_ADDR))
224 
                begin
225 
                        mem_port_A_wen = 1;
226 
                        mem_port_A_address = data_in_changed ?  one_plus_mon_write_address :
227 
                                                                                        (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address);
228 
                        mem_port_A_data_in = data_in_changed ? {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
229 
                                                                                        (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} :
230 
                                                                                                {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
231 
                        next_mon_clones_nr = data_in_changed ? 2 :
232 
                                                                                        (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2);
233 
                        next_mon_write_address = data_in_changed ? one_plus_mon_write_address :
234 
                                                                                        (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address);
235 
                        next_mon_samples_after_trigger=mon_samples_after_trigger+1;
236 
                        next_mon_state=MON_STATE_AFTER_TRIGGER;
237 
                end
238 
                else begin
239 
                                mem_port_A_wen=0;
240 
                                if(mon_write_address < LA_MEM_LAST_ADDR) begin
241 
                                        next_mon_write_address = one_plus_mon_write_address;
242 
                                        next_mon_state = MON_STATE_CLEAN_REMAINING_MEMORY1;
243 
                                end else
244 
                                        next_mon_state = MON_STATE_CLEAN_REMAINING_MEMORY2;
245 
                end
246 
        end
247 
        MON_STATE_CLEAN_REMAINING_MEMORY1:
248 
        begin
249 
                if(mon_write_address < LA_MEM_LAST_ADDR) begin
250 
                        mem_port_A_data_in = LA_MEM_EMPTY_SLOT;
251 
                        mem_port_A_wen = 1;
252 
                        mem_port_A_address = mon_write_address;
253 
                        next_mon_write_address = one_plus_mon_write_address;
254 
                end else begin
255 
                        mem_port_A_wen=0;
256 
                        if(bt_cycled) begin
257 
                                next_mon_state = MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS;
258 
                        end else begin
259 
                                next_mon_write_address = bt_queue_tail_address+1;
260 
                                next_mon_state = MON_STATE_CLEAN_REMAINING_MEMORY2;
261 
                        end
262 
                end
263 
        end
264 
        MON_STATE_CLEAN_REMAINING_MEMORY2:
265 
        begin
266 
                if(mon_write_address < LA_TRIGGER_MATCH_MEM_ADDR) begin
267 
                        mem_port_A_data_in = LA_MEM_EMPTY_SLOT;
268 
                        mem_port_A_wen = 1;
269 
                        mem_port_A_address = mon_write_address;
270 
                        next_mon_write_address = mon_write_address+1;
271 
                end else begin
272 
                        mem_port_A_wen=0;
273 
                        next_mon_state=MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS;
274 
                end
275 
        end
276 
        MON_STATE_SAVE_BT_QUEUE_TAIL_ADDRESS:
277 
        begin
278 
                        // Save bt_queue_tail_address
279 
                        mem_port_A_address = LA_BT_QUEUE_TAIL_ADDRESS;
280 
                        mem_port_A_data_in =
281 
                                {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}},
282 
                                bt_queue_tail_address};
283 
                        mem_port_A_wen = 1;
284 
                        next_mon_state=MON_STATE_SC_RUN;
285 
        end
286 
 
287 
        MON_STATE_SC_RUN:
288 
        begin
289 
                        next_mon_state=MON_STATE_WAIT_SC_DONE;
290 
                        next_sc_run=1;
291 
        end
292 
        MON_STATE_WAIT_SC_DONE:
293 
        begin
294 
                // sc_run must already be 1, when entering state MON_STATE_SEND_CAPTURE.
295 
                if(ack_sc_run)
296 
                        next_sc_run=0;
297 
                if((sc_run == 0) && (sc_done))
298 
                        next_mon_state=MON_STATE_IDLE;
299 
                else
300 
                        next_mon_state=MON_STATE_WAIT_SC_DONE;
301 
        end
302 
 
303 
 
304 
        default: // should never get here
305 
        begin
306 
                next_mon_state=4'bxxxx;
307 
                next_sc_run=1'bx;
308 
                next_mon_write_address={LA_MEM_ADDRESS_BITS{1'bx}};
309 
                next_bt_queue_tail_address={(LA_MEM_ADDRESS_BITS){1'bx}};
310 
                next_mon_samples_after_trigger={LA_MAX_SAMPLES_AFTER_TRIGGER_BITS{1'bx}};
311 
                next_mon_clones_nr={LA_IDENTICAL_SAMPLES_BITS{1'bx}};
312 
                mem_port_A_address={LA_MEM_ADDRESS_BITS{1'bx}};
313 
           mem_port_A_data_in={LA_MEM_WORDLEN_BITS{1'bx}};
314 
           mem_port_A_wen=1'bx;
315 
        end
316 
        endcase
317 
end
318 
 
319 
 
320 
endmodule

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