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[/] [openverifla/] [trunk/] [openverifla_2.4/] [verilog/] [verifla/] [send_capture_of_verifla.v] - Blame information for rev 46

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1 46 laurentiud 
/*
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file: send_capture_of_verifla.v
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license: GNU GPL
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Revision history
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revision date: 20180808-1540
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- include baud_clk_posedge
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revision date: 2007/Jul/4; author: Laurentiu DUCA
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- v01
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*/
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//`timescale 1ns/1ps
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module send_capture_of_verifla(clk, rst_l, baud_clk_posedge,
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        sc_run, ack_sc_run, sc_done,
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        mem_port_B_address, mem_port_B_dout,
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        xmit_doneH, xmitH, xmit_dataH);
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`include "common_internal_verifla.v"
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// SC_states
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parameter
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        SC_STATES_BITS=4,
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        SC_STATE_IDLE=0,
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        SC_STATE_ACK_SC_RUN=1,
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        SC_STATE_SET_MEMADDR_TO_READ_FROM=2,
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        SC_STATE_GET_MEM_OUTPUT_DATA=3,
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        SC_STATE_SEND_OCTET=4,
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        SC_STATE_WAIT_OCTET_SENT=5,
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        SC_STATE_WORD_SENT=6;
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// input
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input clk, rst_l;
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input baud_clk_posedge;
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input sc_run;
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input [LA_MEM_WORDLEN_BITS-1:0] mem_port_B_dout;
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input xmit_doneH;
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// output
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output [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address;
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output xmitH;
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output [7:0] xmit_dataH;
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output ack_sc_run, sc_done;
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reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address;
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reg xmitH;
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reg [7:0] xmit_dataH;
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reg ack_sc_run, sc_done;
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// local
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reg [SC_STATES_BITS-1:0] sc_state, next_sc_state;
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reg [LA_MEM_ADDRESS_BITS-1:0] sc_current_address, next_sc_current_address;
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reg [LA_MEM_WORDLEN_OCTETS-1:0] sc_octet_id, next_sc_octet_id;
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reg [LA_MEM_WORDLEN_BITS-1:0] sc_word_bits, next_sc_word_bits;
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// set up next value
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always @(posedge clk or negedge rst_l)
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begin
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        if(~rst_l)
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        begin
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                sc_state=SC_STATE_IDLE;
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                sc_current_address=0;
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                sc_word_bits=0;
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                sc_octet_id=0;
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        end
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        else
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                if (baud_clk_posedge)
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                begin
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                        sc_state=next_sc_state;
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                        sc_current_address=next_sc_current_address;
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                        sc_word_bits=next_sc_word_bits;
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                        sc_octet_id=next_sc_octet_id;
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                end
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end
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// state machine
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always @(sc_state or sc_run or xmit_doneH
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        // not important but xilinx warnings.
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        or sc_current_address or mem_port_B_dout or sc_word_bits or sc_octet_id)
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begin
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        // implicitly
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        next_sc_state=sc_state;
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        ack_sc_run=0;
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        sc_done=0;
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        xmit_dataH=0;
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        xmitH=0;
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        mem_port_B_address=sc_current_address;
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        next_sc_current_address=sc_current_address;
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        next_sc_word_bits=sc_word_bits;
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        next_sc_octet_id=sc_octet_id;
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        // state dependent
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        case(sc_state)
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        SC_STATE_IDLE:
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        begin
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                if(sc_run)
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                begin
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                        next_sc_state = SC_STATE_ACK_SC_RUN;
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                        next_sc_current_address=LA_MEM_LAST_ADDR;
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                end
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                else
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                        next_sc_state = SC_STATE_IDLE;
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        end
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        SC_STATE_ACK_SC_RUN:
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        begin
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                ack_sc_run=1;
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                next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM;
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        end
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        SC_STATE_SET_MEMADDR_TO_READ_FROM:
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        begin
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                mem_port_B_address=sc_current_address;
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                // next clock cycle we have memory dout of our read.
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                next_sc_state = SC_STATE_GET_MEM_OUTPUT_DATA;
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        end
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        SC_STATE_GET_MEM_OUTPUT_DATA:
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        begin
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                next_sc_word_bits=mem_port_B_dout;
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                // LSB first
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                next_sc_octet_id=0;
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                next_sc_state = SC_STATE_SEND_OCTET;
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        end
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        SC_STATE_SEND_OCTET:
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        begin
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                xmit_dataH=sc_word_bits[7:0];
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                next_sc_word_bits={8'd0, sc_word_bits[LA_MEM_WORDLEN_BITS-1:8]}; //sc_word_bits>>8;
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                xmitH=1;
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                next_sc_octet_id=sc_octet_id+1;
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                next_sc_state = SC_STATE_WAIT_OCTET_SENT;
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        end
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        SC_STATE_WAIT_OCTET_SENT:
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        begin
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                if(xmit_doneH)
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                begin
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                        if(sc_octet_id < LA_MEM_WORDLEN_OCTETS)
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                                next_sc_state = SC_STATE_SEND_OCTET;
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                        else
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                                next_sc_state = SC_STATE_WORD_SENT;
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                end
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                else
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                        next_sc_state = SC_STATE_WAIT_OCTET_SENT;
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        end
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        SC_STATE_WORD_SENT:
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        begin
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                if(sc_current_address > LA_MEM_FIRST_ADDR)
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                begin
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                        next_sc_current_address=sc_current_address-1;
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                        next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM;
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                end
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                else
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                begin
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                        // done sending all captured data
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                        sc_done = 1;
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                        next_sc_state = SC_STATE_IDLE;
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                end
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        end
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        default: // should never get here
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        begin
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                next_sc_state=4'bxxxx;
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                sc_done=1'bx;
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                xmit_dataH=1'bx;
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                xmitH=1'bx;
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                mem_port_B_address={LA_MEM_ADDRESS_BITS{1'bx}};
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                next_sc_current_address={LA_MEM_ADDRESS_BITS{1'bx}};
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                next_sc_word_bits={LA_MEM_WORDLEN_BITS{1'bx}};
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                next_sc_octet_id={LA_MEM_WORDLEN_OCTETS{1'bx}};
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        end
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        endcase
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end
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endmodule

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