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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm2/] [or1200_top_cm2.twr] - Blame information for rev 3

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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm2/ise_or1200_cm2/ise_or1200_cm2.ise
-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm2.twx or1200_top_cm2.ncd
-o or1200_top_cm2.twr or1200_top_cm2.pcf -ucf or1200_top_cm2.ucf
 
Design file:              or1200_top_cm2.ncd
Physical constraint file: or1200_top_cm2.pcf
Device,package,speed:     xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report
 
Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.
 
================================================================================
Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;
 
 
 5987 timing errors detected. (5987 component switching limit errors)
 Minimum period is   2.400ns.
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_du/dbg_ack_o/SR
  Logical resource: or1200_du/dbg_ack_o/SR
  Location pin: OLOGIC_X1Y162.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_10_1/SR
  Logical resource: dwb_biu/wb_adr_o_10_1/SR
  Location pin: OLOGIC_X0Y188.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: dwb_biu/wb_adr_o_11_1/SR
  Logical resource: dwb_biu/wb_adr_o_11_1/SR
  Location pin: OLOGIC_X0Y187.SR
  Clock network: rst_i_IBUF
--------------------------------------------------------------------------------
 
================================================================================
Timing constraint: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH
50%;
 
 
 3922 timing errors detected. (3922 component switching limit errors)
 Minimum period is   2.400ns.
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 1.200ns (Tospwh)
  Physical resource: or1200_pic/intr_cml_1_1/SR
  Logical resource: or1200_pic/intr_cml_1_1/SR
  Location pin: OLOGIC_X0Y74.SR
  Clock network: or1200_pic/intr10
--------------------------------------------------------------------------------
Slack: -0.500ns (period - (min low pulse limit / (low pulse / period)))
  Period: 0.500ns
  Low pulse: 0.250ns
  Low pulse limit: 0.500ns (Tockpwl)
  Physical resource: or1200_pic/intr_cml_1_1/CLK
  Logical resource: or1200_pic/intr_cml_1_1/CK
  Location pin: OLOGIC_X0Y74.CLK
  Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
Slack: -0.500ns (period - (min high pulse limit / (high pulse / period)))
  Period: 0.500ns
  High pulse: 0.250ns
  High pulse limit: 0.500ns (Tockpwh)
  Physical resource: or1200_pic/intr_cml_1_1/CLK
  Logical resource: or1200_pic/intr_cml_1_1/CK
  Location pin: OLOGIC_X0Y74.CLK
  Clock network: clk_i_cml_1_BUFGP
--------------------------------------------------------------------------------
 
 
2 constraints not met.
 
 
Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
 
Timing summary:
---------------
 
Timing errors: 9909  Score: 4391040  (Setup/Max: 0, Hold: 0, Component Switching Limit: 4391040)
 
Constraints cover 0 paths, 0 nets, and 0 connections
 
Design statistics:
   Minimum period:   2.400ns{1}   (Maximum frequency: 416.667MHz)
 
 
------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.
 
Analysis completed Thu Oct 21 14:53:27 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 302 MB
 
 
 

Line No.	Rev	Author	Line
1	2	tobil	`--------------------------------------------------------------------------------`
2			`Release 11.1 Trace (nt)`
3			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
4
5			`C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise`
6			`C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm2/ise_or1200_cm2/ise_or1200_cm2.ise`
7			`-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm2.twx or1200_top_cm2.ncd`
8			`-o or1200_top_cm2.twr or1200_top_cm2.pcf -ucf or1200_top_cm2.ucf`
9
10			`Design file: or1200_top_cm2.ncd`
11			`Physical constraint file: or1200_top_cm2.pcf`
12			`Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)`
13			`Report level: verbose report`
14
15			`Environment Variable Effect`
16			`-------------------- ------`
17			`NONE No environment variables were set`
18			`--------------------------------------------------------------------------------`
19
20			`INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths`
21			`option. All paths that are not constrained will be reported in the`
22			`unconstrained paths section(s) of the report.`
23			`INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on`
24			`a 50 Ohm transmission line loading model. For the details of this model,`
25			`and for more information on accounting for different loading conditions,`
26			`please see the device datasheet.`
27
28			`================================================================================`
29			`Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;`
30
31
32			`5987 timing errors detected. (5987 component switching limit errors)`
33			`Minimum period is 2.400ns.`
34			`--------------------------------------------------------------------------------`
35
36			`Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 0.5 ns HIGH 50%;`
37			`--------------------------------------------------------------------------------`
38			`Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))`
39			`Period: 0.500ns`
40			`High pulse: 0.250ns`
41			`High pulse limit: 1.200ns (Tospwh)`
42			`Physical resource: or1200_du/dbg_ack_o/SR`
43			`Logical resource: or1200_du/dbg_ack_o/SR`
44			`Location pin: OLOGIC_X1Y162.SR`
45			`Clock network: rst_i_IBUF`
46			`--------------------------------------------------------------------------------`
47			`Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))`
48			`Period: 0.500ns`
49			`High pulse: 0.250ns`
50			`High pulse limit: 1.200ns (Tospwh)`
51			`Physical resource: dwb_biu/wb_adr_o_10_1/SR`
52			`Logical resource: dwb_biu/wb_adr_o_10_1/SR`
53			`Location pin: OLOGIC_X0Y188.SR`
54			`Clock network: rst_i_IBUF`
55			`--------------------------------------------------------------------------------`
56			`Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))`
57			`Period: 0.500ns`
58			`High pulse: 0.250ns`
59			`High pulse limit: 1.200ns (Tospwh)`
60			`Physical resource: dwb_biu/wb_adr_o_11_1/SR`
61			`Logical resource: dwb_biu/wb_adr_o_11_1/SR`
62			`Location pin: OLOGIC_X0Y187.SR`
63			`Clock network: rst_i_IBUF`
64			`--------------------------------------------------------------------------------`
65
66			`================================================================================`
67			`Timing constraint: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH`
68			`50%;`
69
70
71			`3922 timing errors detected. (3922 component switching limit errors)`
72			`Minimum period is 2.400ns.`
73			`--------------------------------------------------------------------------------`
74
75			`Component Switching Limit Checks: TS_clk_i_cml_1 = PERIOD TIMEGRP "clk_i_cml_1" 0.5 ns HIGH 50%;`
76			`--------------------------------------------------------------------------------`
77			`Slack: -1.900ns (period - (min high pulse limit / (high pulse / period)))`
78			`Period: 0.500ns`
79			`High pulse: 0.250ns`
80			`High pulse limit: 1.200ns (Tospwh)`
81			`Physical resource: or1200_pic/intr_cml_1_1/SR`
82			`Logical resource: or1200_pic/intr_cml_1_1/SR`
83			`Location pin: OLOGIC_X0Y74.SR`
84			`Clock network: or1200_pic/intr10`
85			`--------------------------------------------------------------------------------`
86			`Slack: -0.500ns (period - (min low pulse limit / (low pulse / period)))`
87			`Period: 0.500ns`
88			`Low pulse: 0.250ns`
89			`Low pulse limit: 0.500ns (Tockpwl)`
90			`Physical resource: or1200_pic/intr_cml_1_1/CLK`
91			`Logical resource: or1200_pic/intr_cml_1_1/CK`
92			`Location pin: OLOGIC_X0Y74.CLK`
93			`Clock network: clk_i_cml_1_BUFGP`
94			`--------------------------------------------------------------------------------`
95			`Slack: -0.500ns (period - (min high pulse limit / (high pulse / period)))`
96			`Period: 0.500ns`
97			`High pulse: 0.250ns`
98			`High pulse limit: 0.500ns (Tockpwh)`
99			`Physical resource: or1200_pic/intr_cml_1_1/CLK`
100			`Logical resource: or1200_pic/intr_cml_1_1/CK`
101			`Location pin: OLOGIC_X0Y74.CLK`
102			`Clock network: clk_i_cml_1_BUFGP`
103			`--------------------------------------------------------------------------------`
104
105
106			`2 constraints not met.`
107
108
109			`Data Sheet report:`
110			`-----------------`
111			`No constraints were found to generate data for the Data Sheet Report section.`
112			`Use the Advanced Analysis (-a) option or generate global constraints for each`
113			`clock, its pad to setup and clock to pad paths, and a pad to pad constraint.`
114
115			`Timing summary:`
116			`---------------`
117
118			`Timing errors: 9909 Score: 4391040 (Setup/Max: 0, Hold: 0, Component Switching Limit: 4391040)`
119
120			`Constraints cover 0 paths, 0 nets, and 0 connections`
121
122			`Design statistics:`
123			`Minimum period: 2.400ns{1} (Maximum frequency: 416.667MHz)`
124
125
126			`------------------------------------Footnotes-----------------------------------`
127			`1) The minimum period statistic assumes all single cycle delays.`
128
129			`Analysis completed Thu Oct 21 14:53:27 2010`
130			`--------------------------------------------------------------------------------`
131
132			`Trace Settings:`
133			`-------------------------`
134			`Trace Settings`
135
136			`Peak Memory Usage: 302 MB`
137
138
139

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[/] [or1200_hp/] [trunk/] [ise/] [ise_cm2/] [or1200_top_cm2.twr] - Blame information for rev 3