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tobil |
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Release 11.1 Trace (nt)
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
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C:/EDAptability/coremultiplier/reference/or1200_new/ise/ise_or1200_cm2_top/ise_or1200_cm2_top/ise_or1200_cm2_top.ise
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-intstyle ise -v 3 -s 1 -fastpaths -xml or1200_top_cm2_top.twx
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or1200_top_cm2_top.ncd -o or1200_top_cm2_top.twr or1200_top_cm2_top.pcf -ucf
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or1200_top_cm2_top.ucf
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Design file: or1200_top_cm2_top.ncd
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Physical constraint file: or1200_top_cm2_top.pcf
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Device,package,speed: xc5vlx50,ff676,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;
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352299 paths analyzed, 11138 endpoints analyzed, 59 failing endpoints
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59 timing errors detected. (59 setup errors, 0 hold errors, 0 component switching limit errors)
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Minimum period is 7.505ns.
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--------------------------------------------------------------------------------
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Slack (setup path): -0.385ns (requirement - (data path - clock path skew + uncertainty))
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Source: or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7 (FF)
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Destination: or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
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Requirement: 7.120ns
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Data Path Delay: 7.327ns (Levels of Logic = 7)
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Clock Path Skew: -0.143ns (1.120 - 1.263)
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Source Clock: clk_i_BUFGP rising at 0.000ns
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Destination Clock: clk_i_BUFGP rising at 7.120ns
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Clock Uncertainty: 0.035ns
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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Total Input Jitter (TIJ): 0.000ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Maximum Data Path: or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X25Y45.AQ Tcko 0.450 or1200_top_cm2i/or1200_dc_top/spr_write_cml_1
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or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1_7
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SLICE_X25Y46.C3 net (fanout=27) 0.614 or1200_top_cm2i/or1200_dmmu_top/or1200_dmmu_tlb/spr_addr_cml_1<7>
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| 59 |
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SLICE_X25Y46.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_cs_cml_1<0>
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| 60 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/eear_sel111
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| 61 |
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SLICE_X26Y44.A5 net (fanout=18) 0.590 or1200_top_cm2i/or1200_cpu/or1200_sprs/N105
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| 62 |
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SLICE_X26Y44.A Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_sprs/sr_cml_1<6>
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| 63 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/eear_sel21
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| 64 |
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SLICE_X27Y30.C6 net (fanout=30) 1.073 or1200_top_cm2i/or1200_cpu/or1200_sprs/N109
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| 65 |
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SLICE_X27Y30.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_except/id_pc_cml_1<7>
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| 66 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>261
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| 67 |
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SLICE_X26Y43.A5 net (fanout=1) 1.099 or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>261
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| 68 |
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SLICE_X26Y43.A Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
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| 69 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
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| 70 |
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SLICE_X26Y43.B6 net (fanout=1) 0.154 N1474
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| 71 |
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SLICE_X26Y43.B Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
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| 72 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
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| 73 |
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SLICE_X26Y46.C6 net (fanout=2) 0.444 or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
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| 74 |
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SLICE_X26Y46.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
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| 75 |
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or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
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| 76 |
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SLICE_X28Y46.A6 net (fanout=4) 0.886 or1200_top_cm2i/rf_dataw<6>
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| 77 |
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SLICE_X28Y46.A Tilo 0.094 pm_dc_gate_o_OBUF
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| 78 |
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or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
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| 79 |
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SLICE_X28Y44.BX net (fanout=2) 0.439 or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
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| 80 |
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SLICE_X28Y44.CLK Tds 0.920 or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
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| 81 |
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or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
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| 82 |
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------------------------------------------------- ---------------------------
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| 83 |
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Total 7.327ns (2.028ns logic, 5.299ns route)
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| 84 |
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(27.7% logic, 72.3% route)
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| 85 |
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| 86 |
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--------------------------------------------------------------------------------
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Slack (setup path): -0.339ns (requirement - (data path - clock path skew + uncertainty))
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| 88 |
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Source: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4 (FF)
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Destination: or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
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| 90 |
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Requirement: 7.120ns
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| 91 |
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Data Path Delay: 7.263ns (Levels of Logic = 7)
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| 92 |
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Clock Path Skew: -0.161ns (1.120 - 1.281)
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| 93 |
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Source Clock: clk_i_BUFGP rising at 0.000ns
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| 94 |
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Destination Clock: clk_i_BUFGP rising at 7.120ns
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| 95 |
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Clock Uncertainty: 0.035ns
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| 96 |
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| 97 |
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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| 98 |
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Total System Jitter (TSJ): 0.070ns
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| 99 |
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Total Input Jitter (TIJ): 0.000ns
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| 100 |
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Discrete Jitter (DJ): 0.000ns
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| 101 |
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Phase Error (PE): 0.000ns
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| 102 |
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| 103 |
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Maximum Data Path: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
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Location Delay type Delay(ns) Physical Resource
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| 105 |
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Logical Resource(s)
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| 106 |
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------------------------------------------------- -------------------
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| 107 |
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SLICE_X26Y45.BQ Tcko 0.450 or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
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| 108 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_4
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| 109 |
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SLICE_X30Y47.D5 net (fanout=64) 0.957 or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<4>
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| 110 |
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SLICE_X30Y47.D Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
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| 111 |
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or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
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| 112 |
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SLICE_X30Y47.B2 net (fanout=1) 0.774 or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
|
| 113 |
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SLICE_X30Y47.B Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
|
| 114 |
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or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux00002232
|
| 115 |
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SLICE_X27Y51.C5 net (fanout=12) 0.946 or1200_top_cm2i/or1200_cpu/or1200_cfgr/N2
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| 116 |
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SLICE_X27Y51.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_rf/rf_addra_reg_cml_1<3>
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| 117 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
|
| 118 |
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SLICE_X26Y43.A6 net (fanout=1) 0.635 or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
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| 119 |
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SLICE_X26Y43.A Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
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| 120 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
|
| 121 |
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SLICE_X26Y43.B6 net (fanout=1) 0.154 N1474
|
| 122 |
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SLICE_X26Y43.B Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
|
| 123 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
|
| 124 |
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SLICE_X26Y46.C6 net (fanout=2) 0.444 or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
|
| 125 |
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SLICE_X26Y46.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
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| 126 |
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or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
|
| 127 |
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SLICE_X28Y46.A6 net (fanout=4) 0.886 or1200_top_cm2i/rf_dataw<6>
|
| 128 |
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SLICE_X28Y46.A Tilo 0.094 pm_dc_gate_o_OBUF
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| 129 |
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or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
|
| 130 |
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SLICE_X28Y44.BX net (fanout=2) 0.439 or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
|
| 131 |
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SLICE_X28Y44.CLK Tds 0.920 or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
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| 132 |
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or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
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| 133 |
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------------------------------------------------- ---------------------------
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| 134 |
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Total 7.263ns (2.028ns logic, 5.235ns route)
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| 135 |
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(27.9% logic, 72.1% route)
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| 136 |
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| 137 |
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--------------------------------------------------------------------------------
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| 138 |
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Slack (setup path): -0.321ns (requirement - (data path - clock path skew + uncertainty))
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| 139 |
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Source: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5 (FF)
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| 140 |
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Destination: or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP (RAM)
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| 141 |
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Requirement: 7.120ns
|
| 142 |
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Data Path Delay: 7.245ns (Levels of Logic = 7)
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| 143 |
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Clock Path Skew: -0.161ns (1.120 - 1.281)
|
| 144 |
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Source Clock: clk_i_BUFGP rising at 0.000ns
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| 145 |
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Destination Clock: clk_i_BUFGP rising at 7.120ns
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| 146 |
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Clock Uncertainty: 0.035ns
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| 147 |
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|
| 148 |
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Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
| 149 |
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Total System Jitter (TSJ): 0.070ns
|
| 150 |
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Total Input Jitter (TIJ): 0.000ns
|
| 151 |
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Discrete Jitter (DJ): 0.000ns
|
| 152 |
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Phase Error (PE): 0.000ns
|
| 153 |
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| 154 |
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Maximum Data Path: or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5 to or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
|
| 155 |
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Location Delay type Delay(ns) Physical Resource
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| 156 |
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Logical Resource(s)
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| 157 |
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------------------------------------------------- -------------------
|
| 158 |
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SLICE_X26Y45.CQ Tcko 0.450 or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
|
| 159 |
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or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1_5
|
| 160 |
|
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SLICE_X30Y47.D6 net (fanout=25) 0.939 or1200_top_cm2i/or1200_cpu/or1200_sprs/spr_addr_cml_1<5>
|
| 161 |
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SLICE_X30Y47.D Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
|
| 162 |
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or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
|
| 163 |
|
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SLICE_X30Y47.B2 net (fanout=1) 0.774 or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux0000271
|
| 164 |
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SLICE_X30Y47.B Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_ctrl/spr_addrimm_cml_1<15>
|
| 165 |
|
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or1200_top_cm2i/or1200_cpu/or1200_cfgr/spr_dat_o_10_mux00002232
|
| 166 |
|
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SLICE_X27Y51.C5 net (fanout=12) 0.946 or1200_top_cm2i/or1200_cpu/or1200_cfgr/N2
|
| 167 |
|
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SLICE_X27Y51.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_rf/rf_addra_reg_cml_1<3>
|
| 168 |
|
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
|
| 169 |
|
|
SLICE_X26Y43.A6 net (fanout=1) 0.635 or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>300
|
| 170 |
|
|
SLICE_X26Y43.A Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
|
| 171 |
|
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or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365_SW0
|
| 172 |
|
|
SLICE_X26Y43.B6 net (fanout=1) 0.154 N1474
|
| 173 |
|
|
SLICE_X26Y43.B Tilo 0.094 or1200_top_cm2i/or1200_immu_top/itlb_sxe_cml_1
|
| 174 |
|
|
or1200_top_cm2i/or1200_cpu/or1200_sprs/to_wbmux<6>365
|
| 175 |
|
|
SLICE_X26Y46.C6 net (fanout=2) 0.444 or1200_top_cm2i/or1200_cpu/sprs_dataout<6>
|
| 176 |
|
|
SLICE_X26Y46.C Tilo 0.094 or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxreg<6>
|
| 177 |
|
|
or1200_top_cm2i/or1200_cpu/or1200_wbmux/muxout<6>
|
| 178 |
|
|
SLICE_X28Y46.A6 net (fanout=4) 0.886 or1200_top_cm2i/rf_dataw<6>
|
| 179 |
|
|
SLICE_X28Y46.A Tilo 0.094 pm_dc_gate_o_OBUF
|
| 180 |
|
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or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>1
|
| 181 |
|
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SLICE_X28Y44.BX net (fanout=2) 0.439 or1200_top_cm2i/or1200_cpu/or1200_rf/rf_dataw<6>
|
| 182 |
|
|
SLICE_X28Y44.CLK Tds 0.920 or1200_top_cm2i/or1200_cpu/or1200_rf/from_rfa_int_cml_1<7>
|
| 183 |
|
|
or1200_top_cm2i/or1200_cpu/or1200_rf/rf_sub_ia/rf_disti/BU2/U0/gen_dp_ram.dpram_inst/Mram_ram7/DP
|
| 184 |
|
|
------------------------------------------------- ---------------------------
|
| 185 |
|
|
Total 7.245ns (2.028ns logic, 5.217ns route)
|
| 186 |
|
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(28.0% logic, 72.0% route)
|
| 187 |
|
|
|
| 188 |
|
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--------------------------------------------------------------------------------
|
| 189 |
|
|
|
| 190 |
|
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Hold Paths: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;
|
| 191 |
|
|
--------------------------------------------------------------------------------
|
| 192 |
|
|
Slack (hold path): 0.313ns (requirement - (clock path skew + uncertainty - data path))
|
| 193 |
|
|
Source: or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0 (FF)
|
| 194 |
|
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Destination: or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0 (FF)
|
| 195 |
|
|
Requirement: 0.000ns
|
| 196 |
|
|
Data Path Delay: 0.324ns (Levels of Logic = 0)
|
| 197 |
|
|
Clock Path Skew: 0.011ns (0.156 - 0.145)
|
| 198 |
|
|
Source Clock: clk_i_BUFGP rising at 7.120ns
|
| 199 |
|
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Destination Clock: clk_i_BUFGP rising at 7.120ns
|
| 200 |
|
|
Clock Uncertainty: 0.000ns
|
| 201 |
|
|
|
| 202 |
|
|
Minimum Data Path: or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0 to or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0
|
| 203 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 204 |
|
|
Logical Resource(s)
|
| 205 |
|
|
------------------------------------------------- -------------------
|
| 206 |
|
|
SLICE_X33Y63.AQ Tcko 0.414 or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1<1>
|
| 207 |
|
|
or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1_0
|
| 208 |
|
|
SLICE_X32Y63.BX net (fanout=2) 0.152 or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r2_cml_1<0>
|
| 209 |
|
|
SLICE_X32Y63.CLK Tckdi (-Th) 0.242 or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3<1>
|
| 210 |
|
|
or1200_top_cm2i/or1200_cpu/or1200_mult_mac/mac_op_r3_0
|
| 211 |
|
|
------------------------------------------------- ---------------------------
|
| 212 |
|
|
Total 0.324ns (0.172ns logic, 0.152ns route)
|
| 213 |
|
|
(53.1% logic, 46.9% route)
|
| 214 |
|
|
|
| 215 |
|
|
--------------------------------------------------------------------------------
|
| 216 |
|
|
Slack (hold path): 0.318ns (requirement - (clock path skew + uncertainty - data path))
|
| 217 |
|
|
Source: or1200_top_cm2i/iwb_biu/wb_adr_o_30 (FF)
|
| 218 |
|
|
Destination: or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30 (FF)
|
| 219 |
|
|
Requirement: 0.000ns
|
| 220 |
|
|
Data Path Delay: 0.356ns (Levels of Logic = 0)
|
| 221 |
|
|
Clock Path Skew: 0.038ns (0.183 - 0.145)
|
| 222 |
|
|
Source Clock: clk_i_BUFGP rising at 7.120ns
|
| 223 |
|
|
Destination Clock: clk_i_BUFGP rising at 7.120ns
|
| 224 |
|
|
Clock Uncertainty: 0.000ns
|
| 225 |
|
|
|
| 226 |
|
|
Minimum Data Path: or1200_top_cm2i/iwb_biu/wb_adr_o_30 to or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30
|
| 227 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 228 |
|
|
Logical Resource(s)
|
| 229 |
|
|
------------------------------------------------- -------------------
|
| 230 |
|
|
SLICE_X3Y55.DQ Tcko 0.414 or1200_top_cm2i/iwb_biu/wb_adr_o<30>
|
| 231 |
|
|
or1200_top_cm2i/iwb_biu/wb_adr_o_30
|
| 232 |
|
|
SLICE_X2Y55.CX net (fanout=2) 0.160 or1200_top_cm2i/iwb_biu/wb_adr_o<30>
|
| 233 |
|
|
SLICE_X2Y55.CLK Tckdi (-Th) 0.218 or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1<31>
|
| 234 |
|
|
or1200_top_cm2i/iwb_biu/wb_adr_o_cml_1_30
|
| 235 |
|
|
------------------------------------------------- ---------------------------
|
| 236 |
|
|
Total 0.356ns (0.196ns logic, 0.160ns route)
|
| 237 |
|
|
(55.1% logic, 44.9% route)
|
| 238 |
|
|
|
| 239 |
|
|
--------------------------------------------------------------------------------
|
| 240 |
|
|
Slack (hold path): 0.322ns (requirement - (clock path skew + uncertainty - data path))
|
| 241 |
|
|
Source: or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26 (FF)
|
| 242 |
|
|
Destination: or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26 (FF)
|
| 243 |
|
|
Requirement: 0.000ns
|
| 244 |
|
|
Data Path Delay: 0.359ns (Levels of Logic = 0)
|
| 245 |
|
|
Clock Path Skew: 0.037ns (0.177 - 0.140)
|
| 246 |
|
|
Source Clock: clk_i_BUFGP rising at 7.120ns
|
| 247 |
|
|
Destination Clock: clk_i_BUFGP rising at 7.120ns
|
| 248 |
|
|
Clock Uncertainty: 0.000ns
|
| 249 |
|
|
|
| 250 |
|
|
Minimum Data Path: or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26 to or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26
|
| 251 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 252 |
|
|
Logical Resource(s)
|
| 253 |
|
|
------------------------------------------------- -------------------
|
| 254 |
|
|
SLICE_X3Y45.DQ Tcko 0.414 or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r<26>
|
| 255 |
|
|
or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r_26
|
| 256 |
|
|
SLICE_X2Y45.CX net (fanout=2) 0.163 or1200_top_cm2i/or1200_ic_top/or1200_ic_fsm/saved_addr_r<26>
|
| 257 |
|
|
SLICE_X2Y45.CLK Tckdi (-Th) 0.218 or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1<27>
|
| 258 |
|
|
or1200_top_cm2i/or1200_ic_top/saved_addr_cml_1_26
|
| 259 |
|
|
------------------------------------------------- ---------------------------
|
| 260 |
|
|
Total 0.359ns (0.196ns logic, 0.163ns route)
|
| 261 |
|
|
(54.6% logic, 45.4% route)
|
| 262 |
|
|
|
| 263 |
|
|
--------------------------------------------------------------------------------
|
| 264 |
|
|
|
| 265 |
|
|
Component Switching Limit Checks: TS_clk_i = PERIOD TIMEGRP "clk_i" 7.12 ns HIGH 50%;
|
| 266 |
|
|
--------------------------------------------------------------------------------
|
| 267 |
|
|
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
|
| 268 |
|
|
Period: 7.120ns
|
| 269 |
|
|
High pulse: 3.560ns
|
| 270 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 271 |
|
|
Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o<0>/SR
|
| 272 |
|
|
Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0/SR
|
| 273 |
|
|
Location pin: OLOGIC_X0Y46.SR
|
| 274 |
|
|
Clock network: rst_i_IBUF
|
| 275 |
|
|
--------------------------------------------------------------------------------
|
| 276 |
|
|
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
|
| 277 |
|
|
Period: 7.120ns
|
| 278 |
|
|
High pulse: 3.560ns
|
| 279 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 280 |
|
|
Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_3/SR
|
| 281 |
|
|
Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_3/SR
|
| 282 |
|
|
Location pin: OLOGIC_X2Y42.SR
|
| 283 |
|
|
Clock network: rst_i_IBUF
|
| 284 |
|
|
--------------------------------------------------------------------------------
|
| 285 |
|
|
Slack: 4.720ns (period - (min high pulse limit / (high pulse / period)))
|
| 286 |
|
|
Period: 7.120ns
|
| 287 |
|
|
High pulse: 3.560ns
|
| 288 |
|
|
High pulse limit: 1.200ns (Tospwh)
|
| 289 |
|
|
Physical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_2/SR
|
| 290 |
|
|
Logical resource: or1200_top_cm2i/iwb_biu/wb_sel_o_0_2/SR
|
| 291 |
|
|
Location pin: OLOGIC_X2Y41.SR
|
| 292 |
|
|
Clock network: rst_i_IBUF
|
| 293 |
|
|
--------------------------------------------------------------------------------
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
1 constraint not met.
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
Data Sheet report:
|
| 300 |
|
|
-----------------
|
| 301 |
|
|
All values displayed in nanoseconds (ns)
|
| 302 |
|
|
|
| 303 |
|
|
Clock to Setup on destination clock clk_i
|
| 304 |
|
|
---------------+---------+---------+---------+---------+
|
| 305 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 306 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 307 |
|
|
---------------+---------+---------+---------+---------+
|
| 308 |
|
|
clk_i | 7.505| | | |
|
| 309 |
|
|
---------------+---------+---------+---------+---------+
|
| 310 |
|
|
|
| 311 |
|
|
|
| 312 |
|
|
Timing summary:
|
| 313 |
|
|
---------------
|
| 314 |
|
|
|
| 315 |
|
|
Timing errors: 59 Score: 5950 (Setup/Max: 5950, Hold: 0)
|
| 316 |
|
|
|
| 317 |
|
|
Constraints cover 352299 paths, 0 nets, and 24617 connections
|
| 318 |
|
|
|
| 319 |
|
|
Design statistics:
|
| 320 |
|
|
Minimum period: 7.505ns{1} (Maximum frequency: 133.245MHz)
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 324 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 325 |
|
|
|
| 326 |
|
|
Analysis completed Thu Oct 21 15:15:09 2010
|
| 327 |
|
|
--------------------------------------------------------------------------------
|
| 328 |
|
|
|
| 329 |
|
|
Trace Settings:
|
| 330 |
|
|
-------------------------
|
| 331 |
|
|
Trace Settings
|
| 332 |
|
|
|
| 333 |
|
|
Peak Memory Usage: 317 MB
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
|
